AD6622AS ,Four-Channel, 75 MSPS Digital Transmit Signal Processor TSPAPPLICATIONSCellular/PCS Base StationsMicro/Pico Cell Base StationsWBCDMAWireless Local Loop Base S ..
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AD6624AABC ,Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)CHARACTERISTICS . . . . . . . . . . . . . . . . 3 SBM0 . . . . . . . . . . . . . . . . . . . . . . ..
AD6624AS ,Four-channel, 80 MSPS digital receive signal processor (RSP)CHARACTERISTICS . . . . . . . . . . . . 4ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . ..
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ADC0816CCJ ,8-Bit P Compatible A/D Converters with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0816CCN ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0816CCN/NOPB ,8-Bit Microprocessor Compatible A/D Converterwith 16-Channel Multiplexer 40-PDIP -40 to 85features a highimpedance chopper stabilized comparator, a 256R• 0V to 5V analog input voltage range ..
ADC0816CJ ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
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AD6622AS
Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
REV.0
Four-Channel, 75 MSPS Digital
Transmit Signal Processor (TSP)
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Wideband Digital IF Parallel Output
Wideband Digital IF Parallel Input
Allows Cascade of Chips for Additional Channels
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
High-Speed CIC Interpolating Filter
NCO Frequency Translation
Worst Spur Better than 100 dBc
Tuning Resolution Better than 0.02 Hz
Real or Complex Outputs
Digital Summation of Channels
Clipped or Wrapped Overrange
Two’s Complement or Offset Binary Output
Separate 3-Wire Serial Data Input for Each Channel
Microprocessor Control
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
WBCDMA
Wireless Local Loop Base Stations
Phase Array Beam Forming Antennas
PRODUCT DESCRIPTIONThe AD6622 comprises four identical digital Transmit Signal
Processors (TSPs) complete with synchronization circuitry and
cascadable wideband channel summation. An external digital-
to-analog converter (DAC) is all that is required to complete a
wide band digital up-converter. On-chip tuners allow the relative
phase and frequency for each RF carrier to be independently
controlled.
Each TSP has three cascaded signal processing elements: a
RAM-programmable Coefficient interpolating Filter (RCF), a
programmable Cascaded Integrator Comb (CIC) interpolating
filter, and a Numerically Controlled Oscillator/tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multichannel wideband transmitters, multiple AD6622s may
be combined using the chip’s cascadable output summation stage.
Each channel provides independent serial data inputs that may
be directly connected to the serial port of DSP chips. User pro-
grammable FIR filters can be used to filter linear inputs.
All control registers and coefficient values are programmed through
a generic microprocessor interface. Two microprocessor bus
modes are supported. All inputs and outputs are LVCMOS
compatible. All outputs are LVCMOS and 5 V TTL compatible.
AD6622–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSNOTESThis specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC stages,
maximum switching of input data, and maximum VDD of 3.3 V. In an actual application the power will be less; see the Thermal Management section of the data sheet
for further details.GSM interpolation = 120 at 65 MHz, 4 channels active, IS-136 interpolation = 2560 at 62.208 MHz, 4 channels active. WBCDMA interpolation = 64, 4 channels
interleaved at 61.44 MHz.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1
(CLOAD = 40 pF, all outputs unless specified)
AD6622tHDS
tHRW
tSAM
tHAM
tACCFAST
tACCMEDIUM
MODE MNM Read Timing:
tSAM
tHA
tZD
tDD
tDDTACK
tACCFAST
tACCMEDIUM
NOTESAll Timing Specifications valid over VDD range of 2.4 V to 3.3 V.
Specifications subject to change without notice.
Figure 1.Parallel Output Switching Characteristics
Figure 2.Serial Port Switching Characteristics
Figure 3.Wideband Input Timing
Figure 4.SYNC Timing Inputs
Figure 5.INM Microport Write Timing Requirements
Figure 6.INM Microport Read Timing Requirements
AD6622
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.
2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1
3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER
VERSUS A RAM REGISTER.
4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.
R/W (WR)
DS (RD)
A[2:0]
D[7:0]
DTACK
(RDY)
tHDSFigure 7.MNM Microport Write Timing Requirements
1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.
2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1
3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER
VERSUS A RAM REGISTER.
4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.
R/W (WR)
DS (RD)
A[2:0]
D[7:0]
DTACK
(RDY)
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +3.6 V
Input Voltage . . . .–0.3 V to VDD +0.3 V (Not 5 V Tolerant)
IN[17:0], QIN, OEN
Input Voltage . . . . . . . . . . . . .–0.3 V to +3.6 V (5 V Tolerant)
CLK, RESET, DS, R/W, MODE, A[2:0], D[7:0], SYNC, TRST,
TCK, TMS, TDI, SDINA, SDINB, SDINC, SDIND
Output Voltage Swing . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . .125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . .280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the devices at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS128-Lead MQFP:
θJA = 33°C/W, No Airflow
θJA = 27°C/W, 200 LFPM Airflow
θJA = 24°C/W, 400 LFPM Airflow
θJC = 5.5°C/W
Thermal measurements made in the horizontal position on a
2-layer board.
EXPLANATION OF TEST LEVELS100% Production Tested.
II.100% Production Tested at 25°C, and Sample Tested at
Specified Temperatures.
III.Sample Tested Only.
IV.Parameter Guaranteed by Design and Analysis.Parameter is Typical Value Only.
VI.100% Production Tested at 25°C, and Sample Tested at
Temperature Extremes.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6622 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD6622
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD6622
THEORY OF OPERATIONAs digital-to-analog converters (DACs) achieve higher sampling
rates, analog bandwidth, and dynamic range, it becomes increas-
ingly attractive to accomplish the first IF stage of a transmitter
in the digital domain. Digital IF signal processing provides
repeatable manufacturing, higher accuracy, and more flexibility
than comparable high-dynamic-range analog designs.
The AD6622 Four-Channel Transmit Signal Processor (TSP) is
designed to bridge the gap between DSPs and high-speed DACs.
The wide range of interpolation factors in each filter stage makes
the AD6622 useful for creating both narrowband and wideband
carriers in a high-speed sample stream. The high-resolution NCO
allows flexibility in frequency planning and supports both digital
and analog air interface standards. The RAM-based architec-
ture allows easy reconfiguration for multimode applications.
The interpolating filters remove unwanted images of signals
sampled at a fraction of the wideband rate. When the channel of
interest occupies far less bandwidth than the wideband output
signal, rejecting out-of-band noise is called “processing gain.”
For large interpolation factors, this processing gain allows a
14-bit DAC to express the sum of multiple 16-bit signals sampled
at a lower rate without significantly increasing the noise floor
about each carrier. In addition, the programmable RAM coeffi-
cient stage allows anti-imaging, and static equalization functions
to be combined in a single, cost-effective filter.
The high-speed NCO can be used to tune a quadrature sampled
signal to an IF channel, or the NCO can be directly frequency-
modulated at an IF channel. Multicarrier phase synchronization
pins and phase offset registers allow intelligent management of
the relative phase of the independent RF channels. This capability
supports the requirements for phased array antenna architec-
tures and management of the wideband peak/power ratio to
minimize clipping at the DAC.
noise. The wideband ports can be configured for real or quadra-
ture outputs. Quadrature sampled outputs (I and Q) are limited
to half the master clock rate on the shared output bus.
FUNCTIONAL OVERVIEWThe following descriptions explain the functionality of each of
the core sections of the AD6622. Detailed timing, application,
and specifications are described in detail in their respective por-
tions of the data sheet.
SERIAL DATA PORTThe AD6622 has four independent Serial Ports (A, B, C, and
D) of which accepts data to its own channel (1, 2, 3, or 4) of
the device. Each serial port has three pins: SCLK, SDFS, and
SDIN. The SCLK and SDFS pins are outputs that provide
serial clock and framing. The SDIN pins are inputs that accept
channel data. The serial ports do not accept configuration or
control inputs. The serial ports do not accept external clock
or framing signals, although it is possible to synchronize the
AD6622 serial ports to meet an external timing requirement.
The serial clock output, SCLK, is created by a programmable
internal counter that divides down the master clock. When the
channel is reset, SCLK is held low. SCLK starts on the first
rising edge of CLK after Channel Reset is removed (D0 through
D3 of External Address 4). Once active, the SCLK frequency is
determined by the master CLK frequency and the SCLK divider,
according to the equation below. The SCLK divider is a 5-bit
unsigned value located in Channel Register 0x0D. The user must
select the SCLK divider to ensure that SCLK is fast enough to
accept full input sample words at the input sample rate. See the
design example at the end of this section. The maximum SCLK
frequency is 1/2 of the master clock frequency. The minimum
SCLK frequency is 1/64 of the master clock frequency.
Figure 9.Functional Block Diagram
The serial data frame sync output, SDFS, is pulsed high for one
SCLK cycle at the input sample rate. The input sample rate is
determined by the master clock divided by channel interpolation
factor. If the SCLK rate is not an integer multiple of the input
sample rate, the SDFS will continually adjust the period by one
SCLK cycle in order to keep the average SDFS rate equal to the
input sample rate. When the channel is in sleep mode, SDFS is
held low. The first SDFS is delayed by the channel reset latency
after the Channel Reset is removed. The channel reset latency
varies dependent on channel configuration.
The serial data input, SDIN, accepts 32-bit words as channel
input data. The 32-bit word is interpreted as two 16 bit two’s
complement quadrature words, I followed by Q, MSB first.
The first bit is shifted into the serial port starting on the second
rising edge of SCLK after SDFS goes high, as shown by the
timing diagram below.
Figure 10.Serial Port Switching Characteristics
As an example of the serial port operation, consider a CLK fre-
quency of 62.208 MSPS and a channel interpolation of 2560.
In that case, the input sample rate is 24.3 kSPS (62.208 MSPS/
2560), which is also the SDFS rate. Substituting, fSCLK ≥ 32 ×
fSDFS into the equation below and solving for SCLKDIVIDER,
we find the maximum value for SCLKDIVIDER according to
Equation 2.(2)
Evaluating this equation for our example, SCLKDIVIDER must be
less than or equal to 39. Since the SCLKDIVIDER channel regis-
ter is a 5-bit unsigned number it can only range from 0 to 31.
Any value in that range will be valid for this example, but if it is
important that the SDFS period is constant, then there is another
restriction. For regular frames, the ratio fSCLK/fSDFS must be equal
to an integer of 32 or larger. For this example, constant SDFS
periods can only be achieved with an SCLK divider of 19.
In conclusion, the SDFS rate is determined by the AD6622 master
clock rate and the interpolation rate of the channel. The SDFS
rate is equal to the channel input rate. The channel interpola-
tion is equal to RCF interpolation times CIC5 interpolation,
times CIC2 interpolation(3)
The SCLK rate is determined by the AD6622 master clock
rate and SCLKDIVIDER. The SCLK is a divided version of the
AD6622 master CLK. The SCLK divide ratio is determined by
PROGRAMMABLE INTERPOLATING RAM
COEFFICIENT FILTER (RCF)Each channel has a fully independent RAM Coefficient Filter
(RCF). The RCF accepts data from the serial port, filters it, and
passes the result to the CIC filter. The RCF implements a FIR
filter with optional interpolation. The FIR filter can produce
impulse responses up to 128 output samples long. The FIR
response may be interpolated up to a factor of 128, although
the best filter performance is usually achieved if the RCF inter-
polation factor is confined to 8 or below.
FIR Filter ImplementationThe RCF accepts quadrature samples from the serial port with a
fixed point resolution of 16 bits each, for I and Q.
Figure 11.RCF Block Diagram
The AD6622 RCF realizes a sum-of-products filter using a poly-
phase implementation. This mode is equivalent to an interpola-
tor followed by a FIR filter running at the interpolated rate. In
Figure 12, the interpolating block increases the rate by the RCF
interpolation factor (LRCF) by inserting LRCF-1 zero valued samples
between every input sample. The next block is a filter with a finite
impulse response length (NRCF) and an impulse response of h[n],
where n is an integer from 0 to NRCF-1.
Figure 12.RCF Interpolation
The difference equation for Figure 12 is written below, where
h[n] is the RCF impulse response, b[n] is the interpolated input
sample sequence at point “b” in Figure 12, and c[n] is the out-
put sample sequence at point “c” in the Figure 12.
(4)
This difference equation can be described by the transfer func-
tion from point “b” to “c” as shown Equation 5.
(5)
The actual implementation of this filter uses a polyphase
decomposition to skip the multiply-accumulates when b[n] is
zero. Compared to the diagram above, this implementation has
the benefits of reducing by a factor of LRCF both the time needed to
calculate an output and the required data memory (DMEM). The
price of these benefits is that the user must place the coefficients
into the coefficient memory (CMEM) indexed by the interpo-
AD6622Select the Impulse Response Length (NRCF) and the Inter-
polation Factor (LRCF). The Impulse Response Length
(NRCF) is limited in three ways: by the available calculation
time, by the data memory size (DMEM), and by the coeffi-
cient memory size (CMEM). The equation below shows
that NRCF is limited to the minimum of these three conditions.
TimeCMEM
RestrictionRestriction (6)
DMEM
Restriction
where:
L = LRCF × LCIC5 × LCIC2The interpolation rate (LRCF) may be any integer of NRCF
ranging from 1 to 128, while meeting the above equation.
Most filter designs can be optimized by choosing the small-
est LRCF that does not compromise the image rejection of
the subsequent CIC filter. The quality of an interpolating
filter is a strong function of the NRCF/LRCF ratio and a weaker
function of NRCF. The best filters are usually achieved by
maximizing NRCF/LRCF (no larger than 16) and then increasing
both NRCF and LRCF by the same ratio until the filter becomes
time or CMEM limited.Once NRCF and LRCF are selected, Channel Register 0x0A
is programmed to NRCF – 1, and Channel Register 0x0C is
programmed to NRCF/LRCF – 1.Determine the Impulse Response. The impulse response
relative to the RCF output rate can be calculated using ordi-
nary FIR design techniques. In most cases, it is desirable to
precompensate the inband frequency roll-off of the CIC fil-
ter that follows. There are no symmetry requirements, so the
RCF can also be used for static phase equalization. The
impulse response must be quantized to 16-bit two’s comple-
ment numbers for the CMEM. The channel center gain and
worst-case peak can be calculated for each of the LRCF phases
(p) according to the equations below. A RCF coarse scale
factor (g) that ranges between 0 and 3 is provided to limit
the gain without excessive loss of resolution in the CMEM.
(7)The channel center gain is the response to a constant full-
scale input at every output phase. The summation is split
into phases because the interpolation of the data insures that
only NRCF/LRCF coefficients can be active for any single output.
For LRCF = 1, there is only one phase and the channel center
gain is the simple sum of all the coefficients, scaled by 2–g. If
the channel center gain is not the same for every value of p,
some or all of the images of the channel center will be
(8)The worst-case peak is calculated similarly to the channel
center gain, except that the input sequence swings from full-
scale positive to full-scale negative to match the polarity of the
coefficient by which it will be multiplied, so that each prod-
uct is positive. This results in a maximal that must be less
than one to guarantee no possibility of wrapping. Note that
when LRCF is greater than one, each phase may produce its
worst-case peak in response to a different input sequence.Programming DMEM and CMEM. The DMEM must be
initialized to all zeros to avoid any unpredictable start-up
transients since a reset does not clear the memory. The
impulse response h[n] must be reordered by phase for the
CMEM as shown in the code below. Several filters with
impulse lengths that total less than 128 can be programmed
into the CMEM simultaneously and selected later using the
RCF offset pointer (ORCF) which is set by Channel Register
0x0B.
/* Reorder Fir Coefficients for AD6622 CMEM */
for (p=0; pfor (k=0; kCMEM[O_RCF + p*N_RCF/L_RCF + k] = C[k*L_RCF +p];
/* End of routine */
Table I.RCF Control Registers
CASCASDED INTEGRATOR COMB (CIC)
INTERPOLATING FILTERThe I and Q outputs of the RCF stage are interpolated in inte-
ger factors by two cascaded integrator comb (CIC) filters. The
CIC section is separated into three discrete blocks: a fifth order
filter (CIC5), a second order filter (CIC2), and a scaling block
(CIC Scaling). The CIC5 and CIC2 blocks each exhibit a gain
that increases with respect to their interpolation factors, LCIC5
and LCIC2. The product of these gains must be compensated for
in a shared CIC Scaling block.
Figure 13.CIC Data Path
CIC ScalingThe CIC5 and CIC2 stages have a baseband gain of LCIC54 ×
LCIC2. The CIC scaling block is used to avoid numeric overflow
in the CIC stages. The CIC scale block reduces the signal level
without truncation or loss of resolution. The overall gain of the
CIC section is given by Equation 9.(9)
The value CIC_Scale may range from 0 to 25, and can be inde-
pendently programmed for each channel at Control Register
0x06. CIC_Scale may be safely calculated according Equation 10
to ensure the net gain through the CIC stages.(10)
The ceil function is the next highest integer. While this normally
constitutes a small loss, it can be recovered in the RCF scaling.
Likewise, if the RCF output level is known to be less than full
scale, the CIC gain can be increased by reducing CIC_Scale.
CIC5The CIC5 is a fifth order interpolating cascaded integrator comb
whose impulse response is completely defined by its interpola-
tion factor, LCIC5. The value LCIC5–1 can be independently
programmed for each channel at location 0x09. While this con-
trol register is 8-bits wide, LCIC5 should be confined to the range
from 1 to 32 to avoid the possibility of internal overflow for
full-scale inputs. The transfer function of the CIC5 is given
by the following equations with respect to the CIC5 output
sample rate, fSAMP5.(11)
This polynomial fraction can be completely reduced as follows,
demonstrating a finite impulse response with perfect phase lin-
earity for all values of LCIC5.
The frequency response of the CIC5 can be expressed as follows.
The initial 1/LCIC5 factor normalizes for the increased rate, which is
appropriate when the samples are destined for a DAC with a
zero order hold output. The maximum gain is (LCIC5)4 at base-
band, but internal registers peak in response to various dynamic
inputs. As long as LCIC5 is confined to 32 or less, there is no
possibility of overflow at any register.(13)
As an example, we will consider an input from the RCF whose
bandwidth is 0.141 of the RCF output rate, centered at base-
band. Interpolation by a factor of five reveals five images, as
shown in Figure 14.
Figure 14.Unfiltered CIC Interpolation Image
The CIC5 rejects each of the undesired images while passing
the image at baseband. The images of a pure tone at channel
center (dc) are nulled perfectly, but as the bandwidth increases
the rejection is diminished. The lower band edge of the first
image always has the least rejection. In this example, the CIC5
is interpolating by a factor of five and the input signal has a band-
width of 0.141 of the RCF output sample rate. The plot below
shows –110 dBc rejection of the lower band edge of the first
image. All other image frequencies have better rejection.
AD6622Table II lists maximum bandwidth that will be rejected to various
levels for CIC5 interpolation factors from 1 to 32. Figure 15
corresponds to the listing in the –110 dB column and the LCIC5
= 5 row. It is worth noting that the rejection of the CIC5 improves
as the interpolation factor increases.
Table II.CIC5 Alias Protection
CIC2The CIC2 is a second-order interpolating cascaded integrator
comb whose impulse response is completely defined by its inter-
polation factor, LCIC2. The value LCIC2–1 can be independently
programmed for each channel at location 0x08. While this con-
trol register is 8 bits wide, LCIC2 should be confined to the ranges
shown by the table below according to the interpolation factor
of the CIC5. Exceeding the recommended guidelines may result in
overflow for input sequences at or near full scale. While relatively
small values of LCIC5 allow for the larger overall interpolation
factors with minimal power consumption, LCIC5 should be maxi-
mized to achieve the best overall image rejection.
Table III.Maximum LCIC2 LimitsThe transfer function of the CIC2 is given by the following
equations with respect to the CIC2 output sample rate, fOUT.(14)
This polynomial fraction can be completely reduced as follows,
demonstrating a finite impulse response with perfect phase lin-
earity for all values of LCIC2.(15)
The frequency response of the CIC2 can be expressed as follows.
The maximum gain is LCIC2 at baseband. The initial 1/LCIC2
factor normalizes for the increased rate, which is appropriate
when the samples are destined for a DAC with a zero order hold
output.(16)
As an example, we will consider an input from the CIC5 whose
bandwidth is 0.0033 of the CIC5 rate, centered at baseband.
Interpolation by a factor of five reveals five images, as shown
below.
