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AD6600AST
Dual Channel, Gain-Ranging ADC with RSSI
REV. 0
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual IF Inputs, 70 MHz–250 MHz
Diversity or Two Independent IF Signals
Separate Attenuation Paths
Oversample RF Channels
20 MSPS on a Single Carrier
10 MSPS/Channel in Diversity Mode
Total Signal Range 90+ dB
30 dB from Automatic Gain-Ranging (AGC)
60 dB from A/D Converter
Range >100 dB After Processing Gain
Digital Outputs
11-Bit ADC Word
3-Bit RSSI Word
2� Clock, A/B Indicator
Single 5 V Power Supply
Output DVCC 3.3 V or 5 V
775 mW Power Dissipation
APPLICATIONS
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
Wireless Local Loop, Fixed Access
PRODUCT DESCRIPTIONThe AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes
two input channels, each with 1GHz input amplifiers anddB of automatic gain-ranging circuitry. Both channels are
sampled with a 450MHz track-and-hold followed by an 11-bit,MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con-
trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to
3.3V or 5V digital processing chips.
The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10MSPS
per channel. In single-channel mode, the full clock rate ofMSPS may be applied to a single carrier.
The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro-
cessor. The AD6620 provides 10dB–25dB of additional pro-
cessing gain before passing data to a fixed- or floating-point DSP.
Driving the AD6600 is simplified by using the AD6630 differen-
tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.
Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.
Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).
Dual Channel, Gain-Ranging
ADC with RSSI
NOISE FILTER
AB_OUT
D10–D0
RSSI [2:0]
CLK2�
DVCCENCENCGNDAVCCB_SELA_SEL
AIN
AIN
BIN
BIN
AD6600–SPECIFICATIONS
DC SPECIFICATIONSRESONANT PORT (FLT, FLT)
NOTESAnalog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.A_SEL and B_SEL should be tied directly to ground or AVCC.Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; TMIN = –40�C, TMAX = +85�C unless otherwise noted.)
(AVCC = 5V, DVCC = 3.3V; TMIN = –40�C, TMAX = +85�C unless otherwise noted.)
AD6600
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1
(AVCC = 5V, DVCC = 3.3V; ENC and ENC = 20 MSPS; TMIN = –40�C, TMAX = +85�C unless otherwise noted.)ENCODE INPUTS (ENC, ENC)
2× CLOCK OUTPUT (CLK2×)
OUTPUT RISE/FALL TIMES
NOTESSee AD6600 Timing Diagrams.All switching specifications tested by driving ENC and ENC differentially.Several timing specifications are a function of Encode high time, tENCH; these specifications are shown in the data tables and timing diagrams. Encode duty cycle
should be kept as close to 50% as possible.Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.The 2× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2× are
referenced to 2.0V crossing.This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.Output rise time is measured from 20% point to 80% point of total CLK2× voltage swing; output fall time is measured from 80% point to 20% point of total CLK2×
voltage swing.Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage
swing. All outputs specified with 10pF load.
Specifications subject to change without notice.
AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1, 2
(AVCC = 5V, DVCC = 3.3V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40�C, TMAX = +85�C unless otherwise noted.)CLK2×/DATA (D10:0, RSSI2:0)
NOTESSee AD6600 Timing Diagrams.All switching specifications tested by driving ENC and ENC differentially.This specification IS NOT a function of Encode period and duty cycle.This specification IS a function of Encode period and duty cycle.CLK2× referenced to 2.0V crossing; digital output levels referenced to 0.8 V and 2.0V crossings; all outputs with 10 pF load.For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40°C to +85°C.
Specifications subject to change without notice.
AD6600
AC SPECIFICATIONS
(AVCC = 5V, DVCC = 3.3V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; TMIN = –40�C, TMAX = +85�C unless
otherwise noted.)
AD6600–SPECIFICATIONS
AC SPECIFICATIONS (continued)SECOND HARMONIC
THIRD HARMONIC
AD6600
AC SPECIFICATIONS (continued)NOTESAIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70MHz–250MHz specified operating range.
Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results.Analog Input 3dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1 GHz.Measured real and imaginary values using Network Analyzer.Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for full-scale input power is a function of frequency as
shown in previous specification.Full-scale gain tolerance measured at 200 MHz analog input referenced to 6.7dBm nominal full-scale input power. For the gain measurement test, the input signal
level is set to –6dBFS. Tuning port bandwidth is set to 50 MHz.Main channel set to full-scale input power. Diversity channel swept from –20dBFS to –90dBFS.Measurement includes thermal and quantization noise at 70 MHz analog input. Tuning port bandwidth is set to 50 MHz.Test tones at 160.05 MHz and 170.05 MHz.Measurements at –1 dFBS, –6dBFS, and –10dBFS are in highest attenuation mode, RSSI = 101.Each gain-range is checked at ~3dB from RSSI trip point (not in hysteresis); nominally –16dBFS (RSSI = 100), –22dBFS (RSSI = 011), –28dBFS (RSSI = 010),
–35dBFS (RSSI = 001).Measurement at –54 dBFS is in the lowest attenuation mode, RSSI = 000.
Specifications subject to change without notice.
AD6600
ABSOLUTE MAXIMUM RATINGS1NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Pins AIN, AIN, BIN, BIN.Pins ENC, ENC, A_SEL, B_SEL.Pins D10:0, RSSI2:0, AB_OUT, CLK2×.Pins FLT, FLT.Typical thermal impedance (44-lead LQFP); θJC = 16°C/W, θJA = 55°C/W.
EXPLANATION OF TEST LEVELS
Test Level100% Production Tested.
II.100% Production Tested at 25°C and guaranteed by design
and characterization at temperature extremes.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6600 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
AD6600
PIN FUNCTION DESCRIPTIONS*Digital Outputs (D10:D0) in Two’s Complement Format.
PIN CONFIGURATION
DVCC
GND
AVCC
GND
AB_OUT
CLK2�
ENC
ENC
AVCC
GND
BIN
GND
D10 (MSB)D9D8D7D6D5D4D3D2D1D0 (LSB)
AVCC
GND
BIN
FLT
AIN
GND
AVCCAVCC
FLT
AVCC
DVCC
GND
AVCC
GND
RSSI2
RSSI1
RSSI0
B_SEL
A_SEL
AIN
AD6600
DEFINITIONS OF SPECIFICATIONS
Analog BandwidthThe analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB. The bandwidth is determined by the internal
track-and-hold when the filter node is resonated.
Aperture DelayThe delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input-
is sampled.
Aperture Uncertainty (Jitter)The sample-to-sample variation in aperture delay.
Attenuator 3OIPThe third order intercept point of the front end of the AD6600.
It is the point at which the third order products would theoreti-
cally intercept the input signal level if the input level could increase
without bounds. This is measured using the ADC within the
AD6600 while the input is stimulated with dual tones in the
minimum attenuation (i.e., maximum gain) range.
Channel IsolationThe amount of signal leakage from one channel to the next
when one channel is driven with a full-scale input, and the other
channel is swept from –20 dBFS to –90dBFS with a frequency
offset. The leakage is measured on the side with the smaller signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input ImpedanceThe real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage RangeThe peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential NonlinearityThe deviation of any code width from an ideal 1 LSB step.
Differential Resonant Port ResistanceThe resistance shunted across the resonant port (nominally
630Ω). Used to determine the filter bandwidth and gain of
that stage.
Encode Pulsewidth/Duty CyclePulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications
define an acceptable Encode duty cycle.
Full-Scale Gain ToleranceUnit-to-unit variation in full-scale input power.
Full-Scale Input PowerExpressed in dBm. Computed using the following equation:
Gain Matching (Input A:B)Variation in full-scale power between A and B inputs.
Harmonic Distortion, 2ndThe ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, 3rdThe ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral NonlinearityThe deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion RateThe encode rate at which the SNR of the lowest analog signal fre-
quency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion RateThe encode rate at which parametric testing is performed.
Noise (For Any Range Within the ADC)where:is the input impedance,is the full-scale of the device for the frequency in question,
SNRis the value for the particular input level,
Signalis the signal level within the ADC reported in dB below
full scale. This value includes both thermal and quanti-
zation noise.
Range-Range Gain ToleranceThe gain error in the RSSI attenuator ladder from one range to
the next.
Range-Range Phase ToleranceThe phase error in the RSSI attenuator ladder from one range
to the next.
Differential Resonant Port CapacitanceThe capacitance between the two resonant pins. Used to deter-
mine filter bandwidth and resonant frequency.
RSSI Gain StepThe input amplitude span between taps of the RSSI (received
signal strength) attenuator ladder. Ideally each stage should
span 6 dB of input power.
RSSI HysteresisThe amount of movement in the RSSI switch points, depending
on the direction of approach. Hysteresis prevents unnecessary
RSSI toggling when input signal power is near a threshold.
Signal-to-Noise Ratio (Without Harmonics)The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Worst Other SpurThe ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
AD6600 TRANSFER FUNCTION
AIN LEVEL – dBFS
SNR
dB
–80–70–60–50–40–30–20–10Figure 1.SNR vs. Input Power
AD6600
EQUIVALENT CIRCUITS Figure 2.Analog Input Stage (Channel A Shown;
Channel B Is Equivalent)
GND
GND
AVCC
GND
B_SEL
A_SELFigure 3.A_SEL, B_SEL Input Mode Pins
Figure 4.Digital Outputs
Figure 5.Resonant (LC Noise Filter) Port
Figure 6.Encode Inputs
Figure 7.CLK2�, AB_OUT Outputs
