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AD6472BS
2 pair/1 pair ETSI compatible HDSL analog front end
REV.0
2 Pair/1 Pair ETSI Compatible
HDSL Analog Front End
FUNCTIONAL BLOCK DIAGRAM
TX_GAIN
VCXO
FEATURES
Integrated Front End for Single Pair or Two Pair HDSL
Systems
Meets ETSI Specifications
Supports 1168 Kbps and 2.32 Mbps
Transmit and Receive Signal Path Functions
Receive Hybrid Amplifier, PGA and ADC
Transmit DAC, Filter and Differential Outputs
Programmable Filters
Control and Ancillary Functions
Timing Recovery DAC
Normal Loopback and Low Power Modes
Simple Interface-to-Digital Transceivers
Single 5 V Power Supply
Power Consumption: 320 mW—(Excluding Driver)
Package: 80-Lead MQFP
Operating Temperature: –408C to +858C
GENERAL DESCRIPTIONThe AD6472 is a single chip analog front end for two pair or
single pair HDSL applications that use 1168 Kbps or 2.32 Mbps
data rates.
The AD6472 integrates all the transmit and receive functional
blocks together with the timing recovery DAC.
The digital interface is designed to support industry standard
digital transceivers.
While providing the full analog front end for ETSI standards
(two pair or single pair HDSL applications) the AD6472 sup-
ports other applications because the architecture allows for
bypassing the functional blocks.
The normal, low power, and loopback modes and the digital
interface combine to make the AD6472 simple to integrate into
systems.
AD6472–SPECIFICATIONS(TA = TMIN to TMAX unless otherwise noted)TRANSMIT CHANNEL
POWER SUPPLY VOLTAGE
NOTES
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed in this section may cause permanent damage to the
device. This is a stress rating only, functional operation of the device at these or
any other conditions above those in the operation section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Thermal Characteristics80-Lead Plastic Quad Flatpack Package . . . . . . .θJA = 45°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6472 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
PIN CONFIGURATION
AD6472
PIN CONFIGURATIONS
Circuit DescriptionThe AD6472 is an HDSL analog front end for either 2-pair or
single pair applications.
Transmit ChannelThe AD6472 receives, from a DSP transceiver core, a serial 2s
complement data stream. The data are 16-bit words and the
MSB is received first.
The 12-bit DAC converts the digital data to an analog signal.
Although HDSL uses four level 2B1Q modulation, the 12-bit
DAC is necessary because of the linearity requirements of the
echo canceling circuit.
The active filters have dynamic tuning and selectable filter
corners that meet transmit mask requirements for both two-pair
and single pair applications. A 6 dB attenuation option is in-
cluded as part of the filter to increase the driver output dynamic
range. Bypassing the active filter means giving up the 6 dB
option, and reduces the maximum TX output voltage to
2 V p-p diff.
The filtered transmit signal is then processed by the driver
amplifier. The DAC output controls the driver output level.
The designer can choose to bypass the driver amplifier; in this
case the driver amplifier will be powered down, and the TX
output will be at the TX_LPF_OUT pins.
The AD6472 meets the requirements of the ETSI masks (both
frequency and time domains for pulse shape). This includes the
worst case in RTR/TM 3036.
Table I.Transmit SpectraFigure 1.2-pair Transmit Pulse Shape Mask Normalized
Figure 2.Single Pair Transmit Pulse Shape Mask Normalized
AD6472
Table III.
Table IV.Configuration Control
Receive Channel
Hybrid AmplifierThe hybrid amplifier performs balanced to unbalanced
conversion.
Programmable Gain Amplifier (PGA)The PGA can be programmed to amplify the receive signal
from between –6 dB and 9 dB. Refer to Table II for PGA gain
control information.
Figure 3.
Transmit and Receive FiltersRefer to Table III for transmit and receive channels filter
control information. The receive channel filters meet ETSI
requirements.
Analog-to-Digital Converter (ADC)The receive channel ADC has a pipeline architecture with 12-
bit resolution. The ADC can be clocked at 2320 kHz, maxi-
mum. Output data is provided in 2s complement form.
Timing Recovery D/AThe AD6472 has an integrated D/A converter to control an
external VCXO used for timing recovery. The D/A is 7 bits and
monotonic. The D/A accepts 7 bits inverted format input data
serially with the MSB first.
Configuration ControlTable IV presents control information that you use to configure
the AD6472.
Table II.
