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AD6426XST
Enhanced GSM Processor
Enhanced GSM ProcessorFEATURES
Complete Single Chip GSM Processor
Channel Codec Subsystem including
Channel Coder/Decoder
Interleaver/De-interleaver
Encryption/Decryption
Control Processor Subsystem including
16-bit Control Processor (H8/300H)
Parallel and Serial Display Interface
Keypad Interface
EEPROM Interface
SIM-Interface
Universal System Connector Interface
Interface to AD6425
Control of Radio Subsystem
Programmable backlight duty cycle
Real Time Clock with Alarm
Battery ID Chip Interface
DSP Subsystem including
16-bit DSP with ROM coded firmware for
Full rate Speech Encoding/Decoding (GSM 06.10)
Enhanced Full Rate Speech
Encoding/Decoding (GSM 06.60)
Equalization with 16-state Viterbi (Soft Decision)
DTMF and Call Progress Tone Generation
Power Management of Mobile Radio
Slow Clocking scheme for low Idle Mode current
Ultra Low Power Design
On-chip GSM Data Services up to 14.4 kbit/s
JTAG Test Interface
2.4V to 3.3V Operating Voltage
144-Lead LQFP and 144-Lead PBGA packages
APPLICATIONS
GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS)
Compliant to Phase 1 and Phase 2 specifications
GENERAL DESCRIPTIONThe AD6426 Enhanced GSM Processor (EGSMP) is the
central component of the highly integrated AD20msp425 GSM
Chipset. Offering a low total chip count, low bill of materials
cost and long talk and standby times, the chipset offers
designers a straightforward route to a highly competitive
product in the GSM/DCS1800 market.
The EGSMP performs all the baseband functions of the Layer
1 processing of the GSM air interface. This includes all data
encoding and decoding processes as well as timing and radio
sub-system control functions.
The EGSMP supports full rate and enhanced full rate speech
traffic as well as a full range of data services including F14.4.
Figure 1. Functional Block Diagram
In addition, the EGSMP supports both A5/1 and A5/2
encryption algorithms as well as operation in non-encrypted
mode.
The EGSMP integrates a high performance 16-bit
microprocessor (Hitachi H8/300H), that supports all the GSM
terminal software, including Layer 1, 2 and 3 of the GSM
protocol stack, the MMI and applications software such as
data services, test and maintenance.
The use of the standard H8 processor allows the use of HIOS,
the Hitachi real time kernel, as well as a full range of software
development tools including C compilers, debuggers and in-
circuit emulators. The EGSMP also integrates a high
performance 16-bit Digital Signal Processor (DSP), which
provides speech transcoding and supports all audio functions
in both transmit and receive. In receive it equalizes the
received signal using a 16-state (Viterbi) soft decision
equalizer.
The EGSMP interfaces with all the peripheral sub-systems of
the terminal, including the keypad, memories, display driver,
SIM, DTE and DTA data services interface and radio. It also
has a general purpose interface that can be used to support an
external connection to a car kit or battery charger.
The EGSMP interfaces with the AD6425 or the AD6421
Voiceband/Baseband Codec through a dedicated serial port.
ORDERING GUIDE
eliminary Technical InformationAD6426Table of Contents
GENERAL DESCRIPTION...................................................1
PIN FUNCTIONALITY ( Normal Mode)...............................4
OVERVIEW..........................................................................7
FUNCTIONAL PARTITIONING...........................................7
Channel Codec Sub-System...............................................7
Processor Sub-System........................................................8
DSP Sub-System................................................................8
Speech Transcoding.......................................................8
Equalization...................................................................8
Audio Control................................................................8
Tone Generation............................................................8
Automatic Frequency Control (AFC)..............................8
Automatic Gain Control (AGC)......................................8
REGISTERS..........................................................................9
GENERAL CONTROL........................................................14
Clocks.............................................................................14
Slow Clocking.................................................................14
Real Time Clock and Alarm.............................................14
Reset...............................................................................15
Interrupts.........................................................................15
NMI.................................................................................15
Wait................................................................................16
Automatic Booting...........................................................16
Power Control..................................................................16
INTERFACES.....................................................................16
Memory Interface.............................................................16
EEPROM Interface..........................................................16
SIM Interface...................................................................17
Accessory Interface..........................................................17
Universal System Connector Interface..............................18
Operating modes of the USC............................................18
Buffered UART Mode (Booting/Data Services)................18
Keypad / Backlight / Display Interface.............................19
Battery ID Interface..........................................................20
EVBC Interface...............................................................20
Radio Interface................................................................22
Dual Band Control.......................................................22
Tx Timing Control.......................................................23
Rx Timing Control.......................................................24
Synthesizer Control......................................................24
AGC Control................................................................25
TEST INTERFACE.............................................................27
JTAG Port....................................................................27
Debug Port Interface....................................................29
MODES OF OPERATION...................................................29
Normal Mode (Mode A)..................................................29
Emulation Mode (Mode D)..............................................29
FEATURE MODES.............................................................30
DAI Mode........................................................................30
High Speed Logging.........................................................30
SPECIFICATIONS..............................................................32
General............................................................................32
ABSOLUTE MAXIMUM RATINGS...............................32
TIMING CHARACTERISTICS............................................33
Clocks.............................................................................33
Memory Interface.............................................................34
Radio Interface................................................................35
High Speed Logging Interface..........................................36
Data Interface..................................................................37
Test Interface...................................................................38
EVBC Interface ASPORT................................................39
EVBC Interface BSPORT................................................40
EVBC Interface VSPORT................................................41
Parallel Display Interface.................................................42
Serial Display Interface....................................................43
PACKAGING......................................................................44
LQFP Pin Locations.........................................................44
PBGA Pin Locations........................................................45
LQFP Outline Dimensions...............................................47
PBGA Outline Dimensions..............................................48
eliminary Technical InformationAD6426PIN FUNCTIONALITY ( Normal Mode)* Note: Functionality of these pins can be changed under software control.
eliminary Technical InformationAD6426Pin Functionality ( NORMAL MODE)* Note: Functionality of these pins can be changed under software control.
eliminary Technical InformationAD6426Pin Functionality ( NORMAL MODE)* Note: Functionality of these pins can be changed under software control.
eliminary Technical InformationOVERVIEWThe GSM air interface has been formulated to provide high
quality digital mobile communication. As well as supporting
the traffic channels (speech and/or data), the air interface
specifies a number of signaling channels that are used for call
set up and communications between the network infrastructure
and the mobile. These signaling channels provide the mobileecific features such as handover, as well as a number of
other intelligent features.
The GSM system closely follows the OSI 7-layer model for
communications. Specifically, GSM defines Layers 1, 2 and 3
of the protocols. The lowest level being Layer 1, or the
Physical Layer. It is this part of the network processing for
which the EGSMP is responsible, performing some of the
Layer 1 functions in dedicated hardware for minimum powernsumption and some in software for increased flexibility.
Layer 1 covers those signal processing functions required to
format the speech/data for transmission on the physical
medium. Data must be structured to allow for identification,
recovery and error correction so that the information can be
supplied error free to the layer 2 sub-systems and to the traffic
sources. In addition, the physical layer processing includes the
timing of both transmit and receive data, the encryption of
data for security purposes and the control of the Radio sub-
system to provide timing and to optimize the radio frequency
characteristics. An object code license to Layer 1 software is
supplied with the AD20msp425 chipset.
FUNCTIONAL PARTITIONINGThis datasheet gives only an overview about the functionality
of the EGSMP. The EGSMP consists of three main elements;
the Channel Codec and the Control Processor Sub-System
including several interfaces and the DSP as shown in Figure. The Channel Codec is responsible for the Layer 1 channel
coding and decoding of traffic and control information. The
Processor Sub-system supports the software functions of the
protocol stack and interfaces with the bus peripheral sub-
systems of the terminal. The DSP performs the channel
equalization and speech transcoding.
Channel Codec Sub-SystemThe Channel Codec processes data from two principal sources;
traffic and signaling. The former is normally continuous and
the latter determined on demand. Traffic comes in two forms;
speech and user data. The various traffic sources and the
signaling sources are all processed differently at the physical
layer. Speech traffic data is supplied by the speech transcoder
and the remaining data types are sourced from the Control
Processor and interfaced via a dedicated data interface. The
Channel Codec subsystem functional block diagram is shown
in Figure 3.
timed by an internal timebase that maintains accurate timing
of all sub-systems. This timebase is aligned with the on-aireceive signal and all system control signals, both internal and
external, are derived from it.
The physical layer processing can be divided into 4 phases,
two each for up- and downlink. The data in the transmit pathndergoes an ENCODE phase and then a TRANSMIT phase.
Similarly, data in the downlink path is termed the receive data
and it undergoes a RECEIVE phase followed by a DECODE
phase. The buffer between the ENCODE and TRANSMIT
functions is the INTERLEAVE module that holds the data and
permits the building of the transmit burst structure. Similarly
the DEINTERLEAVE module forms the buffer between the
RECEIVE and the DECODE processes.
Each of these four phases is controlled explicitly by thentrol Processor via control registers that define the mode ofperation of each sub-module and the data source they should
process. Typically these control values are updated every
TDMA frame in response to interrupts from the internal
timebase.
The ENCODE process involves the incorporation of errorotection codes. All data is sourced in packets and two forms
of error coding applied; block coding (parity or Fire code) and
convolution coding. The resultant data block is then written to
the INTERLEAVE module where it is buffered in a RAM.
Data is read from the interleave buffer memories contiguously
but written in non-contiguous manner, thereby implementing
the interleaving function. The TRANSMIT process uses afferent time structure now associated with the on-air TDMA
structure. The data is read from the INTERLEAVE module
and formatted into bursts with the requisite timing. This
involves adding fixed patterns such as the tail bits and training
sequence code. The resultant burst is written to the external
Baseband Converter where the modulation is performed and
the output timed to the system timebase before transmission.
eliminary Technical InformationAD6426A feature of the GSM system is the application, as part of the
TRANSMIT process, of data encryption for the purpose of link
security. After the INTERLEAVE module the data may be
encrypted using the prescribed A5/1 or A5/2 encryption
algorithm.
The RECEIVE function requires unmodulated baseband data
from the equalizer. As necessary the data is decrypted and
written to the DEINTERLEAVE module. This is conducted at
TDMA frame rate, although precise timing is not necessary at
this stage.
The DECODING process reads data from the
DEINTERLEAVE module, inverting the interleave algorithm
and decodes the error control codes, correcting and flagging
errors as appropriate. The data also includes a measure of
confidence expressed as two additional bits per received
symbol. These are used in the convolution decoder to improve
the error decoding performance. The resultant data is then
presented to the original sources as determined by the control
programming. The Channel Codec interfaces with the speech
transcoder for speech traffic data and with an equalizer for
recovered receive data. In the AD6426 the equalizer and
speech transcoder are implemented in the DSP.
Processor Sub-SystemThe Processor Sub-System consists of a high performance 16-
bit microcontroller together with a selection of peripheralements. The processor is a version of the Hitachi H8/300H
that has been developed to support GSM applications and
which is well suited to support the Protocol Stack and
Application Layer software.
DSP Sub-SystemThe DSP Sub-System consists of a high performance 16-bit
digital signal processor (DSP) with integrated RAM and ROM
memories. The DSP performs two major tasks: speech
transcoding and channel equalization. Additionally several
support functions are performed by the DSP. The instruction
code, which advises the DSP to perform these tasks, is stored
in the internal ROM. The DSP sub-system is completely self-
contained, no external memory or user-programming is
necessary.
Speech TranscodingIn Full Rate mode the DSP receives the speech data stream
from the EVBC and encodes the data from 104 kbit/s to 13
kbit/s. The algorithm used is Regular Pulse Excitation, with
Long Term Prediction (RPE-LTP) as specified in the 06-series
GSM Recommendations.
In Enhanced Full Rate mode, the DSP encodes the 104 kbit/s
speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC and
repetition bits) as additionally specified in the Phase 2 version
of the 06-series GSM Recommendations. In both modes, the
DSP also performs the appropriate voice activity detection and
discontinuous transmission (VAD/DTX) functions.
Alternatively the DSP receives encoded speech data from the
channel codec sub-system including the Bad Frame Indicator
(BFI). The Speech decoder supports a Comfort Noise Insertion
(CNI) function that inserts a predefined silence descriptor into
the decoding process. The resulting data, at 104 kbit/s, is
transferred to the EVBC.
EqualizationThe Equalizer recovers and demodulates the received signal
and establishes local timing and frequency references for the
mobile terminal as well as RSSI calculation. The equalization
algorithm is a version of the Maximum Likelihood Sequence
Estimation (MLSE) using the Viterbi algorithm. Two
confidence bits per symbol provide additional information
about the accuracy of each decision to the channel codec’s
convolutional decoder. The equalizer outputs a sequence of
bits including the confidence bits to the channel codec sub-
system.
Audio ControlThe DSP subsystem is also responsible for the control of the
audio path. The EVBC provides two audio inputs and two
audio outputs, as well as a separate buzzer output, which are
switched and controlled by the DSP. Furthermore the EVBC
provides for variable gain and sensitivity which is also
controlled by the DSP under command of the Layer 1
software.
Tone GenerationAll alert signals are generated by the DSP and output to the
EVBC. These alerts can be used for the buzzer or for the
earpiece. The tones used for alert signals can be fully defined
by the user by means of a description which provides all the
parameters required such as frequency content and duration of
components of the tone. The tone descriptions are provided by
the Layer 1 software.
Automatic Frequency Control (AFC)The detection of the frequency correction burst provides the
frequency offset between the mobile terminal and the received
signal. This measure is supplied to the Layer 1 software which
then requests a correction of the master clock oscillatorequency via the AFC-DAC in the EVBC. In order to do so
the Layer 1 software includes a transfer function for the
oscillator frequency against the voltage applied. The DSP
provides the measurements for the AFC.
Automatic Gain Control (AGC)The DSP is also responsible for making measurements of the
power in the received signal. This is used for a number of
functions including RSSI measurement, adjacent channel
monitoring and AGC. The Layer 1 software passes theequested gain level to the DSP, which then analyzes the
received signal and generates an AGC control signal.
Depending on the radio architecture, this control signal will be
used in digital form or, converted by the AD6425 in analog
form.
eliminary Technical InformationAD6426REGISTERSThe AD6426 contains 88 Channel Codec Control Registers, 69
H8 Peripheral Registers mapped into the Channel Codec
address space starting at 8000h. All registers are normally
accessed by the Layer 1 software provided with the
AD20msp425 chipset. The user is not expected to read or
write to any registers other than through the Layer 1 software.
Therefore only a limited description of these registers is given
here to ease the understanding of the functional behavior of
the AD6426. Only registers which can be modified or
monitored by the user under control of the Layer 1 software
are shown. The Channel Codec Control Registers are listed in
Table 1, and the H8 Peripheral Control Registers in Table 3
A description of the Channel Codec Control Register contents
is shown in Table 2, and of the H8 Peripheral Registers in
Table 4.
Table 1. CC Control Registers
eliminary Technical InformationAD6426Table 2. CC Control Register ContentsTest Data EnableCalibrate RadioBase Station Identity CodeKeypad ColumnKeypad RowEVBC Serial Port ( 15 : 8 )EVBC Serial Port ( 7 : 0 )Tx Data DelayError CountSynthesizer (31: 24)Synthesizer (23: 16)Synthesizer (15: 8)Synthesizer (7: 0)Backlight Duty Cycle
Deinterleave
SW-ResetInterrupt CounterEVBC Tx Address
eliminary Technical InformationAD6426Table 3. H8 Peripheral Control Registers
eliminary Technical InformationAD6426Table 4. H8 Peripheral Register ContentsTransmit[7:0]Receive[7:0]SCR[7:0]
eliminary Technical InformationAD6426H8 Peripheral Register Contents (Continued)Test Key[7:0]
eliminary Technical InformationAD6426GENERAL CONTROL
Clocks
Clock InputThe AD6426 requires a single 13 MHz, low level clock signal,
which has to be provided at the pin CLKIN. For proper
operation a signal level of 250 mVPP minimum is required.
This feature eases system design and reduces the need for
external clock buffering. Only minimal external components
are required as shown in Figure 4.
The internal clock buffer can accept any regular waveform as
long as it can find voltage points in the signal, for which a
50% duty cycle can be determined. This condition is met for
sinewaves, triangles, or slew-limited square waves. Dedicated
circuitry searches for these points and generates the respective
bias voltage internally.
The external capacitor (1nF) decouples the bias voltage of the
clock signal generated by the oscillator from the internally
generated bias voltage of the clock buffer circuitry.
The LC-filter shown is optional. It ensures, that the input
signal is “well behaved” and sinusoidal. Additionally it filters
out harmonics and noise, that may be on top of the pure 13
MHz signal.
Optional
13 MHz Filter
Clock OutputThe input clock drives both the H8 and the Channel Codec
directly. A gated version, controlled by the Output Clocknable flag in CC Control Register 45, drives the CLKOUT
pin of the EVBC interface. The stand-by state of CLKOUT is
logic zero. The CLKOUT output will be active on reset.
Slow ClockingTo reduce power consumption of AD20msp425 solutions, a
new slow clocking scheme has been designed into the
AD6426. This scheme allows the VCTCXO to be powered
down between paging blocks during Idle Mode and for a
32.768kHz oscillator to keep the time reference during this
period. Only a common 32.768kHz watch crystal is required to
take advantage of this scheme. As in previous generations,
power consumption is also kept to a minimum using
asynchronous design techniques and by stopping all
unnecessary clocks.
Layer 1 software and logic built into the AD6426 are
responsible for maintaining synchronization and calibration of
the slow clock and ensure the validity of the time reference
under all circumstances. The active-high OSC13MON output
is prevented from becoming inactive if the 32.768kHz signal is
not present. The following table describes the functionality of
the relevant pins.
The following table lists the recommended specification for a
32kHz crystal.
than one year of resolution. The RTC module contains a
32.768kHz on chip oscillator buffer designed for very low
power consumption and a set of registers for a timer, alarm,
control and status functions.
The RTC circuit is supplied by two sources; a VDDRTC
supply pin and the main system VDD. It is the handset
designer’s responsibility to provide suitable switching
between the main system VDD and a backup supply to ensure
the RTC module is permanently powered.
The VDDRTC pin is intended to interface to a backup battery
circuit or charge holding network in order for the RTC to
maintain timing accuracy when the main battery is removed
and the handset is powered down.
The user can set an alarm time at which the handset powers
up. If an alarm time is set, the current time matches the alarm
time, and the power on alarm feature is enabled, the handset is
powered up by asserting the PWRON pin for a period of
approximately 2 seconds.
eliminary Technical InformationAD6426The VDDRTC was designed to interface with either a:· Lithium Battery orCapacitor in the range of 0.4F (maximum for ~24 hours
standby) to 8mF (~30 minutes standby)
ResetThe AD6426 is reset by setting the RESET pin to GND. This
will reset the H8-processor, the Channel Codec, the internal
DSP as well as the LCD controller interface and Boot ROM
logic. Both the DSP and the Channel Codec will be held in
reset until the RESET register is written to by the H8. At least
50 CLKIN cycles must elapse before deasserting the RESET
pin and at least a further 100 cycles before writing to the
RESET register.
For reset at power up, the DSP must be held in reset for at
least 2000 clock cycles to enable the internal PLL to lock.
The RESET CC Control Register 35 contains the following
flags:
Additionally 8 functional modules can be reset under control
of the two SWRESET registers:
The JTAG circuitry is reset by a power-on reset mechanism.
Further resets must be done by asserting the TMS input high
for at least five TCK clock cycles. When JTAG compliance is
re-enabled, the JTAG is reset forcing the AD6426 into its
normal mode of operation, selecting the BYPASS register byefault.
The H8 fetches its program start vector from location 0x0000
in segment zero. This can either be from external ROM or
internal Boot ROM, depending on the status of the
BOOTCODE pin.
InterruptsThe interrupts are controlled by the two CC Control Registers
77 and 78. These registers only apply to Emulation Mode, in
that they define which of the interrupts are able to assert
CCIRQ2.
NMIThe non-maskable interrupt NMI input of the H8 processor is
multiplexed with the IRQ6 pin. IRQ6 is the default function,
though asserting the NMI Select flag in CC Control Register 7
will select the NMI function. When not selected, NMI will be
tied off high internally, though it remains driven by the JTAG
port for test purposes. The signal is programmable to be edge
or level sensitive. It defaults to falling edge. The edge polarity
can be changed by programming the H8. However, if
FLASHPWD is used then the same setting must be applied to
CC Control Register 77. The default of zero implies falling
edge sensitive. This way NMI going active can correctly de-
assert FLASHPWD. The NMI can be used for test purposes or
user defined features. NMI is capable of bringing the control
processor out of software standby mode and therefore suitable
for functions such as alarm inputs, power management etc.
During manufacture the NMI can be used to trigger special
test code.
In addition NMI can be generated internally thus freeing up
the IRQ6 PIN. In this mode the TXENABLE NMI will occur
on the rising edge of the TXENABLE as seen at the pin. The
H8 should be set up for a negative edge NMI in this case.
Setting bit 5 in the SERDISPLAY/NMI H8 Peripheral Control
Register 106 to a ONE enables the TXENABLE NMI.
However, the Layer 1 Software must program the external INT
pin to INT6 before the register bit is set.
eliminary Technical InformationAD6426WaitThe H8 microprocessor WAIT input signal can be controlled
externally by programming the FLASHPWD pin to switch to
the WAIT input function. Setting the flag FLASHPWD Disable
in CC Control Register 77 to 1 and GPO11 Select to 0,
transforms the FLASHPWD output pin into a WAIT input pin.
External devices driving WAIT must drive high on reset and
until the software has changed the FLASHPWD pin to the
WAIT function.
Automatic BootingTo allow download of FLASH memory code into the final
system, the AD6426 provides a small dedicated routine to
transfer code through the Data Interface into the FLASH
memory. This routine is activated by asserting the
BOOTCODE pin.
Power ControlThe AD6426 and Layer 1 software is optimized to minimize
the mobile radio power consumption in all modes of operation.
Two power control registers are dedicated for activating and
deactivating functional modules:
INTERFACESThe GSM Processor provides eleven external interfaces for
dedicated purposes:
1. Memory Interface
2. EEPROM Interface
3. SIM Interface
4. Accessory Interface
5. Universal System Connector Interface
6. Keypad / Backlight / Display Interface
7. Battery ID Interface
8. Voiceband/Baseband Converter (EVBC)
Interface
9. Radio Interface
10. Test Interface
11. Debug Interface
Memory InterfaceThe memory interface of the AD6426 serves two purposes.
Primarily, it provides the data, address, and control lines for
the external memories (RAM and ROM / FLASH Memory).condly, the data and address lines are used to interface with
the display. The pins of the memory interface are listed in
Table 5.
Table 5. Memory Interface
The HWR and LWR pins can be configured to function as
UBS and LBS, respectively, by setting the SRAM16 bit (bit 0)
of the MEMIF H8 Peripheral Control Register 80. This bit is
reset at power-up. When configured as UBS and LBS, these
pins facilitate access of 16-bit SRAM in conjunction with the
Read/Write Strobes.
The pin FLASHPWD is automatically asserted low when the
H8 enters the Software Standby Mode, and de-asserted when
an interrupt causes the H8 to exit the Software Standby Mode.
This allows the use of “deep power down mode” for certain
FLASH memories. Also the entire data bus is driven lowring software standby mode.
EEPROM InterfaceThe AD6426 provides a 3-wire interface to an external
EEPROM by using three GPIOs of the control processor.
Table 6 shows the functionality of these three pins.
Table 6. EEPROM Interface
eliminary Technical InformationAD6426The EEPROM interface is controlled entirely through software
via the EEPROM register. This allows support for everyesired timing and protocol.
SIM InterfaceThe AD6426 allows direct interfacing to the SIM card via a
dedicated SIM interface. This interface consists of 7 pins as
shown in Table 7. Some applications may not require
SIMPROG and SIMCARD; thus SIMPROG and SIMCARD
can be re-used as additional general purpose I/O-pins.
Table 7. SIM InterfaceI
Accessory InterfaceThe AD6426 provides 12 interface pins listed in Table 8 for
control of peripheral devices such as a car kit. However, two
general purpose I/O-pins of the Accessory Interface areoposed to be used for additional control of the radio section
as described in the Radio Interface chapter.
Table 8. Accessory Interface
All GPIO pins start up as inputs. GPIO8 and GPIO9 arentrolled by flags in CC Control Register 79. When the
GPIOn OP Enable flag is set to 0, the GPIOn Data flag
reflects the input pin state when read and writing to GPIOn
Data has no effect.
When the GPIOn OP Enable flag is set to 1, the GPIOn Data
flag returns when read the last value written to it and controls
the GPIOn pin when written to it.
Additional general purpose inputs and outputs are available
under software control. The following pins shown in Table 9
become general purpose inputs/outputs or outputs.
Table 9. Additional GPIO / GPO Pins
If the pins SIMCARD and SIMPROG are not required in the
application, they can be used as additional H8 programmable
general purpose inputs or outputs.
Setting GPO10 Select (CC Control Register 7) to 1, will
transform the pin ADD20 into a general purpose output
allowing the pin to be directly controlled via GPO10 Data.
By setting GPO11 Select (CC Control Register 77) to 1 and
FLASHPWD Disable to 1, the pin FLASHPWD becomes a
general purpose output. The pin state is toggled by setting the
GPO11 Data flag.
To increase the flexibility of the AD6426, three pins in the
Radio Interface are multiplexed within GPO functions. The
pins multiplexed are: SYNTHEN1, AGCA and AGCB, with
the default function being the Radio Interface. The mode of
these pins is controlled by the Channel Codec Register
ccGPO.
The GPO[n]Sel bit selects the function of the pin. Setting
GPO[n]Sel to one will enable the pin to be controlled by the
GPO[n] bit. The GPO[n]Sel bit will override any other pin
function selection.
eliminary Technical InformationAD6426To transform the TXPA pin into a general purpose output, set
TXPA Width = 0 (CC Control Register 75 and 76), then use
TxPA Polarity flag (CC Control Register 6) to toggle pin state.
To use the CALIBRATERADIO pin as a general purposetput, set the AUTOCALIBRATE flag to zero and use the
CALIBRATERADIO flag to toggle pin state.
Universal System Connector InterfaceA typical GSM handset requires multiple serial connections to
provide data during normal phone operation, manufacturing,
testing, and debug. In an ideal case many of these functions
could be combined into a single multi-purpose systemnnector. For example, the USC port can be used for:Flash code download for manufacturing and updates· Booting - UART interface used to download programs to
H8 memory· DAI Acoustic mode testing - connects System Simulator
(SS) directly to EVBC· DAI Transcoding mode - connects SS to 6426 for speech
codec testing· External DTA (Data Terminal Adapter) - asynchronous
link for MSDI interface· RS232 port - for on-board data services· H8 debug / monitor· Hands-free operation - time shared VBC and H8 portReceive I/Q monitoring
The Universal System Connector (USC) of the 6426 isesigned such that no external glue logic is required to achieve
this multi-purpose functionality. Furthermore, since the USC’s
function is related to the voiceband and I/Q data serial ports,
the USC block is also responsible for the correct configuration
of these serial data streams.
The actual system connector has the minimum number of pins
to achieve the needed functionality. This save system pins, andllows for a more reliable connector from a manufacturing and
mechanical standpoint. The USC defines a 5 pin connector
that multiplexes asynchronous, synchronous, and modem
control signals as needed:
Operating modes of the USC
Buffered UART Mode (Booting/Data Services)This mode attaches the H8/DSP buffered UART to the USC,
bringing out either the serial bit rate clock or the Modemntrol Signal RI. This is the default mode when the phone is
powered up.
The BOOTCODE pin will be latched on RESET high. If
BOOTCODE is high at RESET, execution begins from the
Boot ROM which will configure the buffered UART to
download the FLASH programming code into RAM. The
FLASH program itself is also downloaded via the UART.
An external Data Terminal Adapter can also be used. In this
case Data Services are done external to the phone and then
transferred to and from the H8. With the external Data
Terminal Adapter, the serial bit rate clock output is selected
for USCRI pin.
This mode can be used for a variety of H8 debug tasks as the
UART can be used to simply shift debug information out.
Note that when in this mode if the handshake signals and
serial bit clock are not required, the RTS and RI pins can be
used as extra GPO, and the CTS pin used as an extra GPI.
Time-shared Mode (Multi-switch)This mode allows time multiplexed communication with both
the H8 and DSP. This is most useful as a hands-free solution,
but can be used for other purposes also e.g., DAI Transcoding
Testing. This mode is used for DAI testing of the DSP’s
speech transcoder in which the DSP’s SPORT0 is connected to
the USC through the Multi-switch.
DAI Acoustic Mode TestingThis mode is used for DAI testing of the 6425’s phone’s
acoustic properties. The VSPORT of the 6425 connects to the
USC through the Multi-switch.
IQ MonitoringThis mode is used for testing the RF receive path and allows
access to the I and Q samples from the AD6425. The AD6425
signals are simply routed to the USC. This means that the
clock and frame sync are provided by the 6425 as well.
16 bit ModeThis mode connects the synchronous data path to the
SDIR/SDOR H8 Peripheral Control Registers, giving the H8
full access to the synchronous port bandwidth. This allows a
fast synchronous communication to an external device, and is
intended to be used for a fast download mechanism.
eliminary Technical InformationKeypad / Backlight / Display InterfaceThis interface combines all functions of display and keyboard
as shown in Table 10.
Table 10. Keypad / Backlight / Display Interface
By providing 4 keypad-column outputs (open drain, pull low)
and 6 keypad-row inputs the AD6426 can monitor up to 24
keys. Additionally, an extra column can be implemented by
using the “ghost column” method for a total of 30 keys. The
H8 processor is interrupted whenever a key is pressed. The
KEYPADCOL pins are connected to the Keypad Column3-0
flags in the KEYPAD COLUMN CC Control Register 9.
The six KEYPADROW pins are connected to the Keypad Row
5-0 flags in the KEYPADROW CC Control Register 10.
One backlight control output (BACKLIGHT) is provided,
which can be modulated to provide the same perceived
brightness for a reduced average current. Switching frequency
as well as duty cycle can be modified to compensate for
ambient lighting levels and changing battery voltage.
The BACKLIGHT output is activated by setting the
Backlight1 flag in the SYSTEM CC Control Register 0.
Once activated, an internal PWM circuit can control theequency and the duty cycle of the output signal. The PWMrcuit is enabled by the Modulate1 flag in the BACKLIGHT
CC Control Register 50. To switch the backlight continuously
on, enable the Backlight 1 flag and disable the Modulate 1
flag.
The frequency is determined by the flags
of 4/128 by programming the
in the POWER CONTROL INTERNAL CC Control Register
connec
dedicated control signals (LCDCTL and DISPLAYCS) and
eliminary Technical InformationAD6426Serial Display InterfaceThe serial display interface is compatible with display drivers
by Motorola and Seiko-Epson. The display driver by Motorola
uses an SPI serial bus which requires an inverted or delayed
clock in comparison to the Seiko-Epson type display driver.
In the Motorola mode the data is delayed by one half clock
cycle such that the data is driven on the rising edge of SCLK
instead of on the falling edge.
The serial display interface consists of four pins; a serial data
output (DISPD0), clock (DISPCLK), chip enable (DISPEN)
and address (DISPA0). These pins are multiplexed with
GPIO4, GPIO3, LCDCTL and DISPLAYCS.
Bit 1 (DISP) of the MEMIF H8 Peripheral Control Register 80
controls the configuration of the display interface. With this
set to 0, the parallel display interface is used. Setting this bit
to one enables the use of the serial display interface. This bit
is set to 0 on reset.
Bit 4 (SERDISP MODE) of the SERDISPLAY/NMI H8
Peripheral Control Register 106 controls the serial display
mode. The default setting is Seiko-Epson mode. To enable the
Motorola mode the user must set the register bit to ONE.
Display ResetNo dedicated pin is used to reset the display sub system. It is
recommended that the VBCRESET pin is used for this
function by connecting the Reset input on the display and the
Reset input on the VBC to the AD6426 VBCRESET pin. The
VBC and display cannot be reset independently. However one
of the GPIO pins can be used to reset the display separately.
Battery ID InterfaceThe AD6426 provides a single-wire interface compatible with
the Dallas SemiconductorÔ DS2434or DS2435 Battery
Identification chip. The communication protocol supports three
operations: RESET, READ and WRITE. These operations
permit reading the present status off the battery and writing
updated information to the ID chip. The interface is available
as the BATID function multiplexed on the GPIO5 pin.
Bit 3 (DALLAS EN) of the MEMIF H8 Peripheral Control
Register 80 controls the enabling of the battery ID interface
module. Setting this bit to zero enables the interface, resetting
the bit disables it. This bit is set to one on reset.
EVBC InterfaceThe AD6426 interfaces directly to the Enhanced Voiceband
Baseband Converter AD6425 through the pins shown in Table.The communication is performed through three serial ports:
the Auxiliary Serial Port (ASPORT), the Baseband Serial Port
(BSPORT) and the Voiceband Serial Port (VSPORT). Layer 1
software enables/disables the clock output in order to reduce
system power consumption to a minimum if operation of the
AD6425 is not required. Figure 6 shows the interface between
the AD6426 and the AD6425 as well as to the AD6432 IF
chip.
Table 12. EVBC Interface
FunctionClock Output to EVBC
ASPORT
ASDO
ASOFS
ASCLK
ASDI
BSPORT
BSDO
BSOFS
BSCLK
BSIFS
BSDI
VSPORT
eliminary Technical InformationAD6426Radio InterfaceThe AD6426 Radio Interface has been designed to support
direct connection to the ADI IF-Chips AD6432, while
providing full backwards compatibility to existing radio
designs interfacing to the AD20msp410 and AD20msp415.
Additionally the AD6426 Radio Interface supports radiorchitectures based on Siemens, TTP/Hitachi or Philips RF
chipsets.
The Radio Interface of the AD6426 consists of 16 dedicated
output pins listed in Table 13. Together with two optional
general purpose I/O-pins they provide a flexible interface to a
variety of radio architectures for both 900 MHz and 1800/1900
MHz operation.
Dual Band ControlTo support dual band handsets BANDSELECT[1:0] signals
are provided. BANDSELECT0 is multiplexed with GPIO[2],
with the default function of this being GPIO[2].
BANDSELECT1 is multiplexed with GPIO[1], the default
function being GPIO[1].
For Dual Band solutions requiring a single band select bit, the
BANDSELECT0 function is enabled by asserting the BAND
EN bit. In order to set BANDSELECT0 high/low and cause
the radio module to operate in the appropriate band, the least
significant bit (bit 0) of the relevant 32 bit register for
Dynamic Synthesizer 1 must be written, i.e. different values
may be set for Rx, Tx and Monitor but only for Dynamic
Synthesizer 1.
BANDSELECT0 is sampled internally and is valid from the
beginning of data serialization, both for on demand
(immediate) loading and ordinary interrupt driven loading.
The BANDSELECT0 signal will remain in this known state
until the next time there is any serialization of data for
Dynamic Synthesizer 1, when a new sample will be taken of
the least significant bit of the 32 bit synthesizer register
currently being serialized.
Full control is provided over the number of bits to be shifted
out to the synthesizer and so it is intended that this bit count
will always be less than 32 when using the BANDSELECT0
feature in order to prevent shifting the control bit out.
BANDSELECT0 is gated with RADIO POWER CONTROL to
ensure that whenever the RADIO is off, BANDSELECT0 is
forced to a low state.
For Dual Band Solution requiring two band select bits, one for
GSM900, and one for DCS1800, then both BANDSELECT0
and BANDSELECT1 are enabled by asserting both the BAND
EN and DCSSEL EN bits. The BANDSELECT0 output is
driven as in the single enable mode (described above), and the
BANDSELECT1 output is the inverted output of the raw
BANDSELECT0 output (prior to gating with RADIO POWER
CONTROL), gated with RADIO POWER CONTROL to force
a low output when the Radio is off.
In order to increase the flexibility of the AD6426, three pins in
the Radio Interface are multiplexed with GPO functions. The
pins multiplexed are: SYTHEN1, AGCA and AGCB, with the
default function being the Radio Interface.
The mode of these pins is controlled by the new ccGPO
Channel Codec Register:
The GPO[n]Sel bit selects the function of the pin. Setting
GPO[n]Sel to one will enable the pin to be controlled by the
GPO[n] bit. The GPO[n]Sel bit will override any other pin
function selection.
Generic PinsThe following three pins have the same functionality in all
types of radio architectures:
RADIOPWRCTL
This output signal is typically used to power down the
oscillators and prescalers during Idle mode and is directly
controlled by the Radio Power Control flag in the POWER
CONTROL EXTERNAL CC Control Register 45.
Table 13. Radio Interface
FunctionBANDSELECT1
eliminary Technical InformationAD6426GPIO6 - VBIAS
This general purpose I/O pin can be used to control thewering up/down of a separate voltage converter, which may
be needed to provide the supply voltage for GaAs RF Powermplifiers. Significant turn-on time of the voltage converterequires an early power-up signal, which is provided by
GPIO6. This control is achieved entirely through a software
driver, without hardware support. Since this function is not
needed for all radio solutions, the GPIO pin can be used for
other functions if not required.
GPIO7 - ANTENNASELECT
This general purpose I/O pin can be used to switch between
two different antennas, as required, when the mobile radio is
used in conjunction with a car-kit with external antenna. This
control is achieved entirely through a software driver, without
hardware support. Since this function is not needed for alladio solutions, the GPIO pin can be used for other functions if
not required.
Tx Timing ControlThe following 5 radio interface pins serve different functions
depending on the radio architecture:
TXPHASE
The purpose of this signal is to switch PLLs between Rx and
Tx modes. The signal is generated under control of the flags
TXPHASE Enable and TXPHASE Polarity of the RADIO
CONTROL CC Control Register 2.
In radios based on the TTP/Hitachi solution, this signal can be
used to switch the VCO´s.
In radios based on the Siemens or Philips solution, this signal
can be used for control switching PLLs, or band switching
UHF PLLs.
TXENABLE
This signal enables the RF modulator and transmit chainncluding the PA, and controls the TXON-pin of the AD6425.
The signal is generated under control of flag Transmit Enable
of the RADIO CONTROL CC Control Register 2.
TXPA
This signal is used as a power amplifier (PA) enable and/or as
a control signal for the PA control loop. This allows the PA to
be isolated from the supply outside the Tx-slot to save current.
In the PA control loop it can be used to control the dynamics
of the loop. The flag Tx Pa Polarity in the TRAFFIC MODE
CC Control Register 6, provides independent control for the
TXPA signal.
TXPA is derived from the leading edge of TXENABLE signal
shown in Figure 7.
TXENABLE
TXPA
Figure 7. Timing of TXPA
The parameter TD is a programmable delay (0 to 1023 QBIT) to
accommodate the EVBC settling time. TD is therefore a 10 bit
value, accessed via the TXPA OFFSET 1 CC Control Register
73 and the TXPA OFFSET 2 CC Control Register 74.
The parameter TW is a programmable width (0 to 1023 QBIT)
which defines the PA enable time. TW is therefore a 10 bit
value, accessed via the TXPA WIDTH 1 CC Control Register
75 and the TXPA WIDTH 2 CC Control Register 76.
If TW is set to zero, then TXPA will be disabled.
eliminary Technical InformationAD6426Rx Timing ControlRXON
The signal at the output pin RXON is generated by the
function Receive Enable OR Monitor Enable of the RADIO
CONTROL CC Control Register 2. It can be used to enable
the RF receiver and controls the RXON-pin of the AD6425. In
radios based on the Siemens solution this signal would be
connected to the RXON1 input. Additional RXON derived
signals are provided to support this solution.
The type of autocalibration is set in the TRAFFIC MODE CC
Control Register 6
In radios based on the Siemens chipset, this signal wouldnnect to the RXON2 input. The required behavior is enabled
by selecting the Type 1 CalibrateRadio function.
Synthesizer ControlThe radio interface of the AD6426 supports 2 dynamic
synthesizers, with each capable of downloading data onemand.
The two Synthesizer Load Dynamic flags located in the
SYNTH CONTROL CC Control Register 38, will set the
synthesizer interface to load 3 consecutive long-words from
Layer 1. flag in thective
eliminary Technical InformationAD6426The two dynamic synthesizers are programmable as follows,
while each synthesizer may be independently disabled,
through the two Disable Synthesizer flags in the
SYNTHESIZER PROGRAM CC Control Register 72.
SYNTHEN0 : 1
The AD6426 provides enable signals for two independent
synthesizers. These signals are available at the output pins
SYNTHEN0 and SYNTHEN1. The polarities of these signals
are individually programmable; i.e. bit 7 of CC Control
Register 38 is applied to the synthesizer selected by either bit
2 or bit 1 of the same register.
SYNTHDATA and SYNTHCLK
Three Modes can be selected to support different radio
architectures. The selection of the Pin-Mode is done by the
two Pin Mode flags in the SYNTHESIZER PROGRAM CC
Control Register 72 as shown in Table 14.
Table 14. Pin Mode0
The default is Mode 1, which supports TTP/Hitachi Bright
and Philips radio architectures. Mode 2 also supports a Philips
architecture, while Mode 3 supports a Siemens architecture. In
Mode 1, the pins SYNTHDATA and SYNTHCLK have their
original functionality; i.e. SYNTHDATA is the data output
and SYNTHCLK is the clock output of the serial synthesizer
interface. Clock polarity and frequency are programmed in the
SYNTH CONTROL CC Control Register 38.
Table 15. Pin Function in Mode 1
In Modes 2 and 3, the outputs of these two pins are
multiplexed with flags of the internal DSP as indicated in
Table 16. The function of DSPFLAG1 ô Synthesizer Data is
defined as: The output is that of DSPFLAG1 except when the
synthesizer interface is active. In this case the synthesizertput has priority. The same applies to DSPFLAG2 ô
Synthesizer Clock.
Table 16. Pin Function in Modes 2 and 3
AGC ControlAGC programming is achieved in one of three ways:
The first is a gain select approach, whereby the DSPFLAG0
and DSPFLAG1 are used as a 2-bit gain selector (AGCA,
AGCB). This is available in Mode 1 and the flags are under
direct control of the internal DSP and are timing independent
of the synthesizer interface.
Table 17. Pin Function in Mode 1
The second is through the DSP combined with the serialnthesizer interface, as defined in Mode 2. The function of
DSPFLAG0 ô SYNTHEN1 is defined as: The output is that of
DSPFLAG0 except when the synthesizer interface is active.
To support the Philips chipset whereby the AGC and the PLL
are programmed over the same enable line, the AGCA pin is
multiplexed to provide a SYNTHEN1 gated with DSPFLAG0.
This pin would be wired instead of the SYNTHEN1 pin. Since
the DSP would program the AGC during RXON, and thenthesizers are reprogrammed following the end of the active
phase, no conflict can occur.
