AD5532BBC-1 ,32-Channel 14-bit Bipolar Voltage-Output DACspecifications T to T , unless otherwise noted.)SS DD MIN MAXAD5532B-11 2Parameter B Version Unit C ..
AD5532HSABC ,32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interfacespecifications T to T unless otherwise noted.)MIN MAX2 A Version1Parameter Min Typ M ..
AD5533ABC-1 ,32-Channel, 14-Bit Voltage-Output DACspecifications TSS DD MINto T unless otherwise noted.)MAX2 A Version Conditions ..
AD5533BBC-1 ,32-Channel Infinite Sample-and-Holdspecifications T to T , unless otherwise noted.)SS DD MIN MAX1 2Parameter B Version Unit Conditions ..
AD5539JQ , Ultrahigh Frequency Operational Amplifier
AD5541 ,16-Bit Voltage-Output DAC in SO-8 PackageGENERAL DESCRIPTIONCS16-BIT DATA LATCHThe AD5541 and AD5542 are single, 16-bit, serial input,LDACCO ..
AD9630AN ,Low Distortion 750 MHz Closed-Loop Buffer AmpSPECIFICATIONSOutput Offset Voltage +25
AD5532BBC-1
32-Channel 14-bit Bipolar Voltage-Output DAC
REV.A
32-Channel, 14-Bit DAC with Precision
Infinite Sample-and-Hold Mode
FUNCTIONAL BLOCK DIAGRAM
SYNC/CS
CALA4–A0SCLKOFFSET_SEL
DVCC
VIN
DINDOUT
AVCCREFREFOFFS
OFFS
VOUT 31
VOUT 0
TRACK/RESET
BUSY
DACGND
AGND
DGND
SER/ PAR
VDDVSS
FEATURES
High Integration:
32-Channel DAC in 12 mm � 12 mm CSPBGA
Guaranteed Monotonic to 14 Bits
Infinite Sample-and-Hold Capability to �0.018% Accuracy
Infinite Sample-and-Hold Total Unadjusted Error �2.5mV
Adjustable Voltage Output Range
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Output Impedance 0.5 �
Output Voltage Span 10 V
Temperature Range –40�C to +85�C
APPLICATIONS
Automatic Test Equipment
Optical Networks
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTIONThe AD5532B is a 32-channel, voltage output, 14-bit DAC with
an additional precision infinite sample-and-hold mode. The
selected DAC register is written to via the 3-wire serial inter-
face and VOUT for this DAC is then updated to reflect the new
contents of the DAC register. DAC selection is accomplished via
address bits A0–A4. The output voltage range is determined by
the offset voltage at the OFFS_IN pin and the gain of the
output amplifier. It is restricted to a range from VSS + 2 V to
VDD – 2 V because of the headroom of the output amplifier.
The device is operated with AVCC = +5 V ± 5%, DVCC = +2.7V
to +5.25 V, VSS = –4.75 V to –16.5 V, and VDD = +8 V to +16.5V
and requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS32-channel, 14-bit DAC in one package, guaranteed
monotonic.The AD5532B is available in a 74-lead CSPBGA with a body
size of 12 mm � 12 mm.In infinite sample-and-hold mode, a total unadjusted error of
±2.5 mV is achieved by laser-trimming on-chip resistors.
*. Patent No. 5,969,657; other patents pending.
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V;
DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V;
OFFS_IN = OV; Output Range from VSS + 2 V to VDD – 2 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.)AD5532B–SPECIFICATIONS
AD5532BDIGITAL INPUTS
NOTESSee Terminology section.B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.Input range 100 mV to 2.96 V.Guaranteed by design and characterization, not production tested.AD780 as reference for the AD5532B.Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings section.Guaranteed by design and characterization, not production tested.Output unloaded.
Specifications subject to change without notice.
DAC AC CHARACTERISTICS
ISHA AC CHARACTERISTICS
NOTESSee Terminology section.B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
PARALLEL INTERFACENOTESSee Parallel Interface Timing Diagram.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACEt10
NOTESSee Serial Interface Timing Diagrams.
AD5532B
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications TMIN to TMAX, unless otherwise noted.)AC CHARACTERISTICS
SERIAL INTERFACE TIMING DIAGRAMSFigure 3.10-Bit Write (ISHA Mode and Both Readback Modes)
Figure 4.24-Bit Write (DAC Mode)
SCLK
SYNC
PARALLEL INTERFACE TIMING DIAGRAMFigure 1.Parallel Write (ISHA Mode Only)
Figure 2.Load Circuit for DOUT Timing Specifications
AD5532B
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25°C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . –0.3 V to AVCC + 0.3 V
VIN to AGND, DAC_GND . . . . . . . . –0.3 V to AVCC + 0.3 V
VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead CSPBGA Package, θJA Thermal Impedance . . 41°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation . . . . . . . . . . . . (150°C – TA)/θJA mW3
Max Continuous Load Current at TJ = 70°C,
per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA4
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.This limit includes load power.This maximum allowed continuous load current is spread over eight channels,
with channels grouped as follows:
Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10
Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26
Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29
Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31
For higher junction temperatures, derate as follows:
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532B features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDEAD5532ABC-1*
AD5532ABC-2*
AD5532ABC-3*
AD5532ABC-5*
AD5533ABC-1*
AD5533BBC-1*
*Separate Data Sheet.
PIN CONFIGURATION
74-Lead CSPBGA Ball Configuration*NC = Not Connected
AD5532B
PIN FUNCTION DESCRIPTIONSNOTESInternal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
DAC CODE
OUTPUT
VOLTAGE16k
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
2.963V70mV0V
VOUT
VIN
UPPER
LOWER
