AD5300BRM-AD5300BRT Fast Delivery |IC PHOENIX CO.,LIMITED

AD5300BRT ,+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23applications.to 30 MHz and is compatible with standard SPI™, QSPI™,3. The on-chip output buffer amp ..
AD5300BRT ,+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23CHARACTERISTICSOutput Voltage Range 0 V VDDOutput Voltage Settling Time 4 6 m s 1/4 Scale to 3/4 Sc ..
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AD5300BRM-AD5300BRT
+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23
REV. A
+2.7 V to +5.5 V, 140 mA, Rail-to-Rail Output
8-Bit DAC in an SOT-23
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 8-Bit DAC
6-Lead SOT-23 and 8-Lead mSOIC Packages
Micropower Operation: 140 mA @ 5 V
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.7 V to +5.5 V Power Supply
Guaranteed Monotonic by Design
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
Three Power-Down Functions
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
SYNC Interrupt Facility
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5300 is a single, 8-bit buffered voltage out DAC that
operates from a single +2.7 V to +5.5 V supply consuming
115 mA at 3 V. Its on-chip precision output amplifier allows
rail-to-rail output swing to be achieved. The AD5300 utilizes a
versatile three-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI™, QSPI™,
MICROWIRE™ and DSP interface standards.
The reference for AD5300 is derived from the power supply
inputs and thus gives the widest dynamic output range. The part
incorporates a power-on-reset circuit that ensures that the DAC
output powers up to zero volts and remains there until a valid
write takes place to the device. The part contains a power-down
feature that reduces the current consumption of the device to
200 nA at 5 V and provides software selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery operated equipment.
The power consumption is 0.7mW at 5 V reducing to 1mW in
power-down mode.
The AD5300 is one of a family of pin-compatible DACs. The
AD5310 is the 10-bit version and the AD5320 is the 12-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead mSOIC packages.
PRODUCT HIGHLIGHTSAvailable in 6-lead SOT-23 and 8-lead mSOIC packages.Low power, single supply operation. This part operates from
a single +2.7 V to +5.5 V supply and typically consumes
0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery powered applications.The on-chip output buffer amplifier allows the output of the
DAC to swing rail-to-rail with a slew rate of 1V/ms.Reference derived from the power supply.High speed serial interface with clock speeds up to 30 MHz.
Designed for very low power consumption. The interface
only powers up during a write cycle.Power-down capability. When powered down the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
*Patent pending; protected by U.S. Patent No. 5684481.
AD5300–SPECIFICATIONS
(VDD = +2.7 V to +5.5 V; RL = 2 kV to GND; CL = 500 pF to GND; all specifications
TMIN to TMAX unless otherwise noted)
POWER EFFICIENCY
NOTESTemperature ranges are as follows: B Version: –40°C to +105°C.Linearity calculated using a reduced code range of 4 to 251. Output unloaded.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figure 1.Maximum SCLK frequency is 30 MHz at VDD = +3.6 V to +5.5 V and 20 MHz at VDD = +2.7 V to +3.6 V.
Specifications subject to change without notice.
Figure 1.Serial Write Operation
(VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND . . . . . . .–0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . .+150°C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ Max–TA)/qJAqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .240°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°CSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ Max–TA)/qJAqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .206°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ORDERING GUIDE
*RT = SOT-23; RM = mSOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
AD5300
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
SOT-23 Pin Numbers
3VDD
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion. A typical INL vs. code plot can be seen in Figure 2.
Differential Nonlinearity
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of –1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 3.
Zero-Code Error
Zero-code error is a measure of the output error when zero code
(00 Hex) is loaded to the DAC register. Ideally the output
should be 0 V. The zero-code error is always positive in the
AD5300 because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in LSBs. A plot
of zero-code error vs. temperature can be seen in Figure 6.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FF Hex) is loaded to the DAC register. Ideally the output
should be VDD – 1LSB. Full-scale error is expressed in LSBs. A
plot of full-scale error vs. temperature can be seen in Figure 6.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal ex-
pressed as a percent of the full-scale range.
Total Unadjusted Error
Total Unadjusted Error (TUE) is a measure of the output error
taking into account all the various errors. A typical TUE vs.
code plot can be seen in Figure 4.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in mV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by
1 LSB at the major carry transition (7F Hex to 80 Hex). See
Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV secs and is measured with a full-scale code
change on the data bus, i.e., from all 0s to all 1s and vice versa.
Figure 2.Typical INL Plot
TEMPERATURE – 8C
ERROR – LSBs
MIN INL
MAX DNL
MIN DNL
VDD = +5V
Figure 5.INL Error and DNL Error
vs. Temperature
ISOURCE/SINK – mA
OUT
– V051510
Figure 8.Source and Sink Current
Capability with VDD = 3 V
CODE050250100150200
Figure 3.Typical DNL Plot
TEMPERATURE – 8C–4012004080
ERROR – LSBs
Figure 6.Zero-Scale Error and Full-
Scale Error vs. Temperature
ISOURCE/SINK – mA
OUT
– V051510
Figure 9.Source and Sink Current
Capability with VDD = 5 V
Figure 4.Typical Total Unadjusted
Error Plot
Figure 7.IDD Histogram with
VDD = 3V and VDD = 5V
CODE
IDD
–
100
Figure 10.Supply Current vs. Code
AD5300–Typical Performance Characteristics

Partno	Mfg	Dc	Qty	Available	Descript
AD5300BRM	ADI	N/a	39	avai	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23
AD5300BRT	ADI	N/a	1000	avai	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23
AD5300BRT	AD	N/a	1947	avai	+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23