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Programmable Gains hom 0.1 to 1000
Differential Inputs
Hlgtt CMRR: 110dB min
L ..
AD5212BD ,12-Bit Succesive Approximation High Accuracy A/D ConvertersANALOG
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AD5206BN10-AD5206BR10-AD5206BRU10
4-/6-Channel Digital Potentiometers
4-/6-Channel
Digital Potentiometers
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
256 Position
Multiple Independently Programmable Channels
AD5204—4-Channel
AD5206—6-Channel
Potentiometer Replacement
10 kV, 50 kV, 100 kV
3-Wire SPI-Compatible Serial Data Input
+2.7 V to +5.5 V Single Supply; 62.7 V Dual Supply
Operation
Power ON Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
GENERAL DESCRIPTIONThe AD5204/AD5206 provides four-/six-channel, 256 position
digitally-controlled Variable Resistor (VR) devices. These de-
vices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5204/
AD5206 contains a fixed resistor with a wiper contact that taps
the fixed resistor value at a point determined by a digital code
loaded into the SPI-compatible serial-input register. The resis-
tance between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. The variable resistor offers a completely program-
mable value of resistance between the A terminal and the wiper
or the B Terminal and the wiper. The fixed A-to-B terminal
resistance of 10 kW, 50 kW, or 100 kW has a nominal tempera-
ture coefficient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data word clocked into the serial input register. The first
three bits are decoded to determine which VR latch will be
loaded with the last eight bits of the data word when the CS
strobe is returned to logic high. A serial data output pin at
the opposite end of the serial register (AD5204 only) allows
simple daisy-chaining in multiple VR applications without
additional external decoding logic.
An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 80H into the VR latch.
The AD5204/AD5206 is available in both surface mount
(SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For additional single,
dual, and quad channel devices, see the AD8400/AD8402/
AD8403 products.
AD5204/AD5206–SPECIFICATIONS
ELECTRICAL CHARACTERISTICSNOTESTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I
(VDD = +5 V 6 10% or +3 V 6 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –408C < TA < +858C
unless otherwise noted.)
AD5204/AD5206Resistor Terminals A, B, W, have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test.Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.PDISS is calculated from (IDD · VDD). CMOS logic level inputs result in minimum power dissipation.All dynamic characteristics use VDD = +5 V.See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using both VDD = +3 V or +5 V.Propagation delay depends on value of VDD, RL and CL. See Operation section.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
Ax–Bx, Ax–Wx, Bx–Wx . . . . . . . . . . . . . . . . . . . . . .–20 mA
Digital Input and Output Voltage to GND . . . . . . .0 V, +7 V
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
Package Power Dissipation . . . . . . . . . . . . . .(TJ max–TA)/qJA
Thermal Resistance qJA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . .63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . .70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD5204/AD5206
ORDERING GUIDEThe AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil · 114 mil, 10,488 sq. mil.
Figure 1.Timing Diagram
Figure 2.Detail Timing Diagram
Figure 3.AD5204 Preset Timing Diagram
AD5204 PIN FUNCTION DESCRIPTIONS
AD5206 PIN FUNCTION DESCRIPTIONS
AD5206 PIN CONFIGURATIONA5
VSS
CLK
GND
SDI
VDD
AD5204 PIN CONFIGURATIONNC
VSS
SDO
CLK
SDI
GND
SHDN
VDD
NC = NO CONNECT
AD5204/AD5206
–Typical Performance Characteristics
COMMON MODE – V
SWITCH RESISTANCE –
100Figure 4.Incremental Wiper ON Resistance vs. Voltage
Figure 5.Gain Flatness vs. Frequency
FREQUENCY – Hz1M
NORMALIZED GAIN – dB
100k10kFigure 6.–3 dB Bandwidth vs. Terminal Resistance,
2.7 V Single Supply Operation
Figure 7.–3 dB Bandwidth vs. Terminal Resistance,2.7 V Dual Supply Operation
Figure 8.Bandwidth vs. Code, 10K Version
Figure 9.Bandwidth vs. Code, 50K Version
