AD1871YRS -AD1871YRSZ Fast Delivery |IC PHOENIX CO.,LIMITED

AD1871YRS ,Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADCSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AD1871YRSZ ,Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADCfeatures anMixing ConsolesSPI compatible serial control port that allows for convenientMusical Inst ..
AD1876JN ,16-Bit 100 kSPS Sampling ADCApplicationsBUFFERS11V16-Pin DIP PackageREFCAL8AGNDSerial Twos Complement Output FormatDACLow Input ..
AD1877JR ,Single-Supply 16-Bit Stereo ADCFEATURES FUNCTIONAL BLOCK DIAGRAMSingle 5 V Power SupplySingle-Ended Dual-Channel Analog InputsCLOC ..
AD1878JD ,High Performance 16-/18-Bit Stereo ADCsSpecifications subject to change without notice.–2– REV. 0AD1878/AD1879DIGITAL INPUTSMin Max UnitsV ..
AD1879JD ,High Performance 16-/18-Bit Stereo ADCsSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages ±5VAmbient Temperature 25 °CInp ..
AD8325ARU-REEL ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cablemodems that are designed to the MCNS-DOCSIS upstream –50V = 62dBmVOUTstan ..
AD8326ARE ,High Output Power Programmable CATV Line Driverapplicationssuch as data and telephony cable modems that are designed to–70the MCNS-DOCSIS upstream ..
AD8328ARQ ,5 V Upstream Cable Line DriverCHARACTERISTICSBandwidth (–3 dB) All Gain Codes (1–60 Decimal Codes) 107 MHzBandwidth Roll-Off f = ..
AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications. Typical insertion loss of 0.3 dB @ 10 MHz.2Guaranteed by design and characterizatio ..
AD8328ARQ-REEL ,5 V Upstream Cable Line Driverspecifications make the AD8328 –54@MAX GAIN,ideally suited for MCNS-DOCSIS and Euro-DOCSIS applica- ..
AD8330ARQ ,Low Cost DC-150 MHz Variable Gain AmplifierSPECIFICATIONS V = 0/C, V = 0 V, Differential Operation, unless otherwise noted.)MAG OFSTParameter ..

AD1871YRS -AD1871YRSZ
Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADC
REV. 0
Stereo Audio, 24-Bit,
96 kHz, Multibit �-� ADC
FUNCTIONAL BLOCK DIAGRAM
MCLK
RESET
CLATCH/(M/S)
CCLK/(256/512)
CIN/(DF1)
LRCLK
BCLK
DOUT
DIN
COUT/(DF0)
CASC
XCTRL
VINLP
VINLN
VREF
VINRP
VINRN
CAPLNCAPLPAVDDDVDDODVDD
CAPRNCAPRPAGNDDGND
FEATURES
5.0 V Stereo Audio ADC
with 3.3 V Tolerant Digital Interface
Supports 96 kHz Sample Rates
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
105 dB (Typ) Dynamic Range
Supports 256/512 and 768 � fS Master Clocks
Flexible Serial Data Port
Allows Right-Justified, Left-Justified, I2S Compatible
and DSP Serial Port Modes
Cascadable (up to Four Devices) from a Single DSP
SPORT
Device Control via SPI Compatible Serial Port or
Optional Control Pins
On-Chip Reference
28-Lead SSOP Package
APPLICATIONS
Professional Audio
Mixing Consoles
Musical Instruments
Digital Audio Recorders, Including
CD-R, MD, DVD-R, DAT, HDD
Home Theater Systems
Automotive Audio Systems
Multimedia
PRODUCT OVERVIEW
The AD1871 is a stereo audio ADC intended for digital audio
applications requiring high performance analog-to-digital
conversion. It features two 24-bit conversion channels each
with programmable gain amplifier (PGA), multibit sigma-delta
modulator, and decimation filters. Each channel provides 105 db
of dynamic range, making the AD1871 suitable for applications
such as digital audio recorders and mixing consoles.
Each of the AD1871’s input channels (left and right) can be
configured as either differential or single-ended (two inputs
muxed with internal single-ended-to-differential conversion).
The input PGA features a gain range of 0 dB to 12 dB in steps
of 3 dB. The Σ-∆ modulator features a proprietary multibit
architecture that realizes optimum performance over an audio
bandwidth with standard audio sampling rates of 32 kHz up to
96 kHz. The decimation filter response features very low pass-
band ripple and excellent stop-band attenuation.
The AD1871’s audio data interface supports all common interface
formats such as I2S, left-justified, right-justified as well as other
modes that allow for convenient connection to general-purpose
digital signal processors (DSPs). The AD1871 also features an
SPI compatible serial control port that allows for convenient
control of device parameters and functionality such as sample
word-width, PGA settings, interface modes, and so on.
The AD1871 operates from a single 5 V power supply—with
an optional digital interfacing capability of 3.3 V. It is housed in
a 28-lead SSOP package and is characterized for operation
over the temperature range –40°C to +105°C.
AD1871
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
TEST CONDITIONS UNLESS OTHERWISE SPECIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
ANALOG PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
LOW-PASS DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
HIGH-PASS DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
MASTER CLOCK (MCLK) AND RESET TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DATA INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
CONTROL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DIGITAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
TEMPERATURE RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
TYPICAL PERFORMANCE CURVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Device Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital Decimating Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Input Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CONTROL/STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Control Register I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Control Register II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Control Register III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Peak Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EXTERNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Master/Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MCLK Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Data Format Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MODULATOR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AD1871–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . 5.0 V
Ambient Temperature . . . . . . . . . . . . . . . . . 25∞C
Input Clock (fCLKIN) [256 ¥ fS] . . . . . . . . . . 12.288 MHz
Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . 991.768 Hz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 dB Full Scale (dBFS) (Differential, PGA/MUX Enabled)
Measurement Bandwidth . . . . . . . . . . . . . . . 23.2 Hz to 19.998 kHz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance on Digital Outputs . . . . . 100 pF
Input Voltage High (VIH) . . . . . . . . . . . . . . . 2.4 V
Input Voltage Low (VIL) . . . . . . . . . . . . . . . 0.8 V
Master Mode, Data I2S Justified
ANALOG PERFORMANCE
Dynamic Range
Signal-to-Noise Ratio
Total Harmonic Distortion + Noise
AD1871–SPECIFICATIONS
LOW-PASS DIGITAL FILTER CHARACTERISTICS (fS = 48 kHz)
LOW-PASS DIGITAL FILTER CHARACTERISTICS (fS = 96 kHz)
HIGH-PASS DIGITAL FILTER CHARACTERISTICS (fS = 48 kHz)
HIGH-PASS DIGITAL FILTER CHARACTERISTICS (fS = 96 kHz)
MASTER CLOCK (MCLK) AND RESET TIMING
Figure 1. MCLK/RESET Timing
AD1871
DATA INTERFACE TIMING (STANDALONE MODE–MASTER)
tBLDLY
Figure 2. Master Data Interface Timing
AD1871
DATA INTERFACE TIMING (STANDALONE MODE–SLAVE)
Figure 3. Slave Data Interface Timing
AD1871
DATA INTERFACE TIMING (CASCADE MODE–MASTER)
Figure 4. Master Cascade Interface Timing
DATA INTERFACE TIMING (CASCADE MODE–SLAVE)
Figure 5. Slave Cascade Interface Timing
DATA INTERFACE TIMING (MODULATOR MODE)
AD1871
CONTROL INTERFACE (SPI) TIMING
Figure 7. Control Interface Timing
DIGITAL I/O
Input Leakage (IIH @ VIH = 5 V)
Input Leakage (IIL @ VIL = 0 V)
POWER
*RESET held low.
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
AD1871YRS-REEL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1871 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
AD1871
PIN FUNCTION DESCRIPTIONS
NOTESExternal Control Mode (See pg 11)Modulator Mode (See pg 11)
Pin Function Redefinition in External Control Mode
Pin Function Redefinition in Modulator Mode
AD1871
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a –60 dB input signal
and is equal to (S/[THD+N]) + 60 dB. Note that spurious
harmonics are below the noise with a –60 dB input, so the
noise level establishes the dynamic range. The dynamic range
is specified with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
(S/[THD+N])
The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all other spectral components
in the pass band, expressed in decibels (dB).
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of the actual output to the
expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of the outputs of
the two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per ∞C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
GLOSSARY
ADC—Analog-to-Digital Converter
DSP—Digital Signal Processor
IMCLK—Internal master clock signal, used to clock the deci-
mating filter section. (Its frequency must be 256 ¥ fS.)
MCLK—External master clock signal applied to the AD1871.
Its frequency can be 256, 512, or 768 ¥ fS. MCLK is divided
internally to give an IMCLK frequency that must be 256 ¥ fS.
MODCLK—This is the �-� modulator clock that determines
the sample rate of the modulator. Ideally, it should not exceed
the lower of 6.144 MHz or 128 ¥ fS. The MODCLK is derived
from the IMCLK by a divider that can be selected as /2 or /4.
MUX—Multiplexer
PGA—Programmable Gain Amplifier
FILTER RESPONSES
TPC 1. Sinc Filter Response (AMC = 0)
TPC 2. First Half-Band Filter Response
TPC 3. Comb Compensation Filter Response
TPC 4. Second Half-Band Filter Response
TPC 5. Composite Filter Response (AMC = 0)
TPC 6. Composite Filter Response (Pass Band Section)
(AMC = 0)
AD1871
DEVICE PERFORMANCE CURVES
TPC 7. High-Pass Filter Response, fS = 48 kHz
TPC 8. High-Pass Filter Response, fS = 96 kHz
TPC 9. 1 kHz Tone at –0.5 dBFS, (32 k-Point FFT), fS = 48 kHz
TPC 10. 1 kHz Tone at –20 dBFS, (32 k-Point FFT), fS = 48 kHz
TPC 11. 1 kHz Tone at –60 dBFS, (32 k-Point FFT),
fS = 48 kHz
TPC 12. THD+N vs. Input Amplitude at 1 kHz, fS = 48 kHz

Partno	Mfg	Dc	Qty	Available	Descript
AD1871YRS	AD	N/a	242	avai	Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADC
AD1871YRSZ	ADI	N/a	5	avai	Stereo Audio, 24-bit, 96kHz, Multi-bit Sigma Delta ADC