AD1852JRSZ ,Stereo, 24-Bit, 192KHz, Multibit Sigma Delta DACSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AV , DV ) 5.0 VDD DDAmbient Te ..
AD1853JRS ,Stereo, 24-Bit, 192 kHz, Multibit DACfeatures include an on-chip clickless stereo at-117 dB Signal to Noise (Not Muted) at 48 kHz tenuat ..
AD1853JRSZ , Stereo, 24-Bit, 192 kHz, Multibit DAC
AD1854 ,Stereo, 96 kHz, Multibit Sigma-Delta DACspecifications).ANALOG PERFORMANCEMin Typ Max UnitResolution 20 BitsSignal-to-Noise Ratio (20 Hz to ..
AD1854JRS ,Stereo, 96 kHz, Multibit DACSpecifications Guaranteed 25 °CFunctionality Guaranteed 0 70 °CStorage –55 +125 °CDIGITAL TIMING (G ..
AD1854JRSRL ,Stereo, 96 kHz, Multibit DACSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AV , DV ) 5.0 VDD DDAmbient Te ..
AD8313ARMZ-REEL7 , 0.1 GHz to 2.5 GHz 70 dB Logarithmic Detector/Controller
AD8314 ,0.1Applications section.2Mean and Standard Deviation specifications are available in Table I.3Increased ..
AD8314ACP-REEL ,0.1applications. A setpoint voltage is applied to VSET andment and control of RF signals in the freque ..
AD8314ACP-REEL ,0.1APPLICATIONSwhich averaging of the input waveform occurs.Cellular Handsets (TDMA, CDMA, GSM)RSSI an ..
AD8314ACP-REEL7 ,0.1Applications section.2Mean and Standard Deviation specifications are available in Table I.3Increased ..
AD8314ACP-REEL7 ,0.1100 MHz–2.7 GHz 45 dBaRF Detector/Controller*AD8314
AD1852JRSZ
Stereo, 24-Bit, 192KHz, Multibit Sigma Delta DAC
REV.0
Stereo, 24-Bit, 192 kHz
Multibit SD DAC
FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/18-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and
192 kHz
Multibit Sigma-Delta Modulator with “Perfect
Differential Linearity Restoration” for Reduced Idle
Tones and Noise Floor
Data-Directed Scrambling DAC—Least Sensitive to
Jitter
Differential Output for Optimum Performance
117 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
114 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
117 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
114 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–105 dB THD+N (Mono Application Circuit)
–102 dB THD+N (Stereo)
115 dB Stopband Attenuation
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emp
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
48 kHz Sample Rates
Clock Autodivide Circuit Supports Five Master-Clock
Frequencies*Patents Pending
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
CLOCK
ANALOG
OUTPUTS2
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASISMUTERESETSERIAL
MODE
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEWThe AD1852 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry. Other features include an on-chip stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats including 192kHz as well as 96kHz sample frequen-
cies and 24 bits. It also is backwards compatible by supportingms/15ms digital de-emphasis intended for “Redbook” compact
discs, as well as de-emphasis at 32kHz and 48 kHz sample rate.
The AD1852 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters. The
AD1852 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 oper-
ates from a single 5 V power supply. It is fabricated on a single
monolithic integrated circuit and is housed in a 28-lead SSOP
package for operation over the temperature range 0°C to 70°C.
AD1852–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25°C
Input Clock24.576 MHz (512 · FS Mode)
Input Signal996.11 Hz
–0.5 dB Full Scale
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width20 Bits
Load Capacitance100 pF
Load Impedance47 kW
Input Voltage HI2.4 V
Input Voltage LO0.8 V
ANALOG PERFORMANCE (See Figures)Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (08C TO 708C)High Level Output Voltage (VOH) IOH = 1 mA
AD1852
TEMPERATURE RANGESpecifications subject to change without notice.
POWERSpecifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICSSpecifications subject to change without notice.
GROUP DELAYINT8x Mode
INT4x Mode
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed Over 08C to 708C, AVDD = DVDD = +5.0 V 6 10%)tDMP
tDMH
tDBH
tDBL
tDBP
tDLS
tDDH
AD1852
ABSOLUTE MAXIMUM RATINGS*AVDD to AGND
Digital Inputs
Soldering
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Table I.Serial Data Input Mode
AD1852
SDATA
INPUT
BCLK
INPUT
L/RCLK
INPUTFigure 1.Right-Justified Mode
Figure 2.I2S-Justified Mode
Figure 3.Left-Justified Mode
SDATA
INPUT
L/RCLK
INPUT
BCLK
INPUTFigure 4.Left-Justified DSP Mode
Figure 5.32 · FS Packed Mode
OPERATING FEATURES
Serial Data Input PortThe AD1852’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero (default
at power-up). To control the serial mode using the SPI mode
select bits, the external mode control pins should be grounded.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24. Extra
bits will not cause an error, but they will be truncated internally.
In the right-justified mode, control register Bits 8 and 9 are used
to set the wordlength to 16 bits, 20 bits, or 24 bits. The default
on power- up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4, and 5) should be tied LO.
Serial Data Input ModeThe AD1852 uses two multiplexed input pins to control the mode
configuration of the input data port mode. See Table I.
Figure 1 shows the right-justified mode (16 bits shown). L/RCLK
is HI for the left channel, LO for the right channel. Data is valid
on the rising edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI wordlength control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the eighth bit clock
pulse after the L/RCLK transition. When the wordlength con-
trol bits are set to 20-bit mode, data is accepted starting at
the twelfth-bit clock position. In 16-bit mode, data is accepted
starting at the sixteenth-bit clock position. These delays are
independent of the number of bit clocks per frame, and therefore
other data formats are possible using the delay values described
above. For detailed timing, see Figure 6.
Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-
nel and HI for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left-justified to an L/RCLK transition
but with a single BCLK period delay. The I2S mode can be used
to accept any number of bits up to 24.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any wordlength up to 24 bits, and any number of bit clocks
from two times the word length to 64 bit clocks per frame.
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is valid.
Data is valid on the falling edge of BCLK. The DSP serial port
mode can be used with any wordlength up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first L/RCLK pulse, and
that synchronism is maintained from that point forward.
BCLK
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
SDATA
I2S-JUSTIFIED
MODE
tDBH
tDBL
tDDS
tDDH
tDDS
tDDH
tDDStDDS
tDDHtDDH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)Figure 6. Serial Data Port Timing
AD1852Note that the AD1852 is capable of a 32 · FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
Master Clock Autodivide FeatureThe AD1852 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above. Master clock should be synchronized with L/RCLK but
phase relation between master clock and L/RCLK is not critical.
Figure 7.Serial Control Port Timing
Table II.
SPI REGISTER DEFINITIONSThe SPI port allows flexible control of many chip parameters. It is
organized around three registers; a LEFT-CHANNEL VOLUME
register, a RIGHT-CHANNEL VOLUME register, and a
CONTROL register. Each WRITE operation to the AD1852
SPI control port requires 16 bits of serial data in MSB-first format.
The bottom two bits are used to select one of three registers,
and the top 14 bits are then written to that register. This allows
a write to one of the three registers in a single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incom-
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to clock the data internally into the AD1852.
