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AD1833ASTADN/a39avaiMultichannel 24-Bit, 192 kHz, DAC
AD1833ASTANALOGN/a31avaiMultichannel 24-Bit, 192 kHz, DAC


AD1833AST ,Multichannel 24-Bit, 192 kHz, DACSpecifications subject to change without notice.Parameter Min Typ Max Unit Test ConditionsANALOG PE ..
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AD8300AR ,+3 Volt, Serial Input Complete 12-Bit DACapplications.The AD8300 is specified over the extended industrial (–40

AD1833AST
Multichannel 24-Bit, 192 kHz, DAC
REV.0
Multichannel,
24-Bit, 192 kHz, �-� DAC
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sample Rates on Six Channels and
192 kHz on 2 Channels
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range:110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control Per Channel with 1024-Step
Linear Scale
Software Controllable Clickless Mute
Digital De-Emphasis Processing
Supports 256 � fS, 512� fS, and 768� fS Master
Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
Supports Packed Data Mode (TDM) for DACs
48-Lead LQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theatre Systems
Automotive Audio Systems
Set-Top Boxes
Digital Audio Effects Processors
FUNCTIONAL BLOCK DIAGRAM
AGNDDGNDFILTR FILTD
MCLK
CDATA
CLATCH
CCLK
OUTLP1
OUTLN1
OUTLP2
OUTLN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTRP1
OUTRN1
ZERO FLAGSDVDD1 DVDD2AVDD
RESET
SOUT
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
GENERAL DESCRIPTION

The AD1833 is a complete, high-performance, single-chip, multi-
channel, digital audio playback system. It features six audio
playback channels each comprising a high-performance digital
interpolation filter, a multibit sigma-delta modulator featuring
Analog Devices patented technology and a continuous-time
voltage-out analog DAC section. Other features include an on-chip
clickless attenuator and mute capability, per channel, programmed
through an SPI-compatible serial control port.
The AD1833 is fully compatible with all known DVD formats,
catering for up to 24-bit word lengths at sample rates of 48 kHz
and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the “Redbook”
standard 50 µs/15 µs digital de-emphasis filters at sample rates
of 32 kHz, 44.1 kHz, and 48 kHz.
The AD1833 has a very flexible serial data input port that allows
for glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. The AD1833
can be configured in left-justified, I2S, right-justified, or DSP
serial port compatible modes. The AD1833 accepts serial audio
data in MSB first, two’s complement format. While the AD1833
can be operated from a single 5 V power supply, it also features
a separate supply pin for its digital interface which allows the
device to be interfaced to devices using 3.3 V power supplies.
It is fabricated on a single monolithic integrated circuit and is
housed in a 48-lead LQFP package for operation over the tem-
perature range –40°C to +85°C.
AD1833–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25°C
Input Clock12.288 MHz, (256 × fS Mode)
Input SignalNominally 1 kHz, 0 dBFS (Full Scale)
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width24 Bits
Load Capacitance500 pF
Load Impedance10 kΩ
NOTES
Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
AD1833
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)
AVDD, DVDDx to AGND, DGND . . . . . . . . –0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
LQFP, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 91°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
PIN CONFIGURATION
OUTRP1
OUTRN1
AVDD
AVDD
AGND
AGND
AGND
OUTLP1
OUTLN1
AVDD
AVDD
AGND
AGND
AGND
DGND
DVDD1
ZEROA
ZERO3R
DGND
DVDD2
RESET
ZERO1L
ZERO3LZERO1R
OUTLN2OUTLP2OUTLN3OUTLP3AVDDFILTDFILTRAGNDOUTRP3OUTRN3OUTRP2OUTRN2
ZERO2RCLATCH
CDATA
CCLK
CLK
BCLK
MCLKSDIN1SDIN2SDIN3
SOUT
ZERO2L
AD1833
Figure 1.MCLK and RESET Timing
DIGITAL TIMING (Guaranteed over –40�C to +85�C, AVDD = DVDD = 5.0 V � 10%)

Specifications subject to change without notice.
PIN FUNCTION DESCRIPTIONS
Figure 3.SPI Timing
–0.01�104
TPC 1.Pass Band Response, 8× Mode
–30
�104
–100

TPC 2.Transition Band Response, 8× Mode
TPC 3.Complete Response, 8× Mode
TPC 4.Pass Band Response, 4× Mode
–0.5
�104
TPC 5.40 kHz Pass Band Response, 4× Mode
–30
�104
–100

TPC 6.Transition Band Response, 4× Mode
AD1833–Typical Performance Characteristics
0.51.52.0–160�105
1.02.53.0

TPC 7.Complete Response, 4× Mode
–2.0
�104
1.0

TPC 8.80 kHz Pass Band Response, 2× Mode
TPC 9.Transition Band Response, 2× Mode
TPC 10.Complete Response, 2× Mode
AD1833
FUNCTIONAL DESCRIPTION
Device Architecture

The AD1833 is a 6-channel audio DAC featuring multibit
Sigma-Delta (Σ-∆) technology. The AD1833 features three
stereo converters (giving six channels) where each stereo channel
is controlled by a common bit-clock (BCLK) and synchroniza-
tion signal (L/RCLK).
Interpolator

The interpolator consists of up to three stages of sample rate
doubling and half-band filtering followed by a 16 sample zero
order hold. The sample rate doubling is achieved by zero stuff-
ing the input samples, and a digital half band filter is then used
to remove any images above the band of interest and to bring
the zero samples to their correct values.
By selecting different input sample rates, one, two, or all three
stages of doubling may be switched in. This allows for three
different sample rate inputs. All three doubling stages are used
with the 48 kHz input sample rate, with the 96 kHz input sample
rate only two doubling stages are used, and with the 192 kHz
input sample rate only one doubling stage is used. In each case
the input sample frequency is increased to 384 kHz. The Zero-
Order Hold (ZOH) holds the interpolator samples for upsampling
by the modulator. This is done at a rate 16 times the interpola-
tor output sample rate.
Modulator

The modulator is a 6-bit, second-order implementation and
uses data scrambling techniques to achieve perfect linearity.
The modulator samples the output of the interpolator stage(s) at
a rate of 6.144 MHz.
OPERATING FEATURES
SPI Register Definitions

The SPI port allows flexible control of the devices’ program-
mable functions. It is organized around nine registers; six
individual channel VOLUME registers and three CONTROL
registers. Each WRITE operation to the AD1833 SPI control
port requires 16 bits of serial data in MSB-first format. The four
most significant bits are used to select one of nine registers (seven
register addresses are reserved), and the bottom 10 bits are then
written to that register. This allows a write to one of the nine
registers in a single 16-bit transaction. The SPI CCLK signal is
used to clock in the data. The incoming data should change on
the falling edge of this signal and remain valid during the rising
edge. At the end of the 16 CCLK periods, the CLATCH signal
should rise to latch the data internally into the AD1833. See
Figure 2.
The serial interface format used on the Control Port utilizes a
16-bit serial word as shown in Table I. The 16-bit word is divided
into several fields: Bits 15–12 define the register address,
Bits11 and 10 are reserved and must be programmed to 0,
and Bits 9–0 are the data field (which has specific definitions,
depending on the register selected).
Table I.Control Port Map

NOTESMust be programmed to zero.Bit 15 = MSB
DAC CONTROL REGISTER I
De-Emphasis

The AD1833 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam-
pling rates. The filters may be selected by writing to Control
Bits 9 and 8 in DAC Control Register I, see Table III.
Table III.De-Emphasis Settings
Data Serial Interface Mode

The AD1833’s serial data interface is designed to accept data in
a wide range of popular formats including I2S, right justified
(RJ), left justified (LJ) and flexible DSP modes. The L/RCLK
pin acts as the word clock (or Frame Sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1-3 pins. The serial mode
settings may be selected by writing to Control Bits 7 through 5
in DAC Control Register I, see Table IV.
Table IV.Data Serial Interface Mode Settings
DAC Word Width

The AD1833 will accept input data in three separate word-
lengths—16, 20, and 24 bits. The word-length may be selected
by writing to Control Bits 4 and 3 in DAC Control Register I,
see Table V.
Table V.Word Length Settings
Power-Down Control

The AD1833 can be powered down by writing to Control Bit 2
in DAC Control Register I, see Table VI. The power-down/
reset bit is not latched when the CLATCH is brought high to
latch the entire word, but only after the following low-to-high
CLATCH transition. Therefore, to put the part in power-down,
or to bring it back up from power-down, the command should
be written twice.
Table VI.Power-Down Control
Interpolator Mode

The AD1833’s DAC interpolators can be operated in one of
three modes—8×, 4×, or 2× corresponding with 48 kHz, 96kHz,
and 192 kHz modes respectively. The Interpolator Mode may
be selected by writing to Control Bits 1 and 0 in DAC Control
Register I, see Table VII.
Table VII.Interpolator Mode Settings
Table II.DAC Control I

*Must be programmed to zero.
AD1833
Table VIII.DAC Control II

*Must be programmed to zero.
DAC CONTROL REGISTER II

DAC Control Register II contains individual channel mute
controls for each of the 6 DACs. Default operation (bit = 0) is
muting off. Bits 9 through 6 of Control Register II are reserved
and should be programmed to zero, see Table VIII.
Table IX.Muting Control
DAC CONTROL REGISTER III
Stereo Replicate

The AD1833 allows the stereo information on Channel 1
(SDIN1—Left 1 and Right 1) to be copied to Channels 2 and 3
(Left/Right 2 and Left/Right 3). These signals can be used in an
external summing amplifier to increase potential signal SNR.
Stereo Replicate mode can be enabled by writing to Control
Bit 5, see Table XI. Note that replication is not reflected in
the zero flag status.
Table XI.Stereo Replicate
Table X.DAC Control III

*Must be programmed to zero.
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