PCA9534BS ,8-bit I2C-bus and SMBus low power I/O port with interruptGeneral descriptionThe PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose paral ..
PCA9534BS3 ,8-bit I2C-bus and SMBus low power I/O port with interruptFeatures2n 8-bit I C-bus GPIOn Operating power supply voltage range of 2.3 V to 5.5 Vn 5 V tolerant ..
PCA9534D ,8-bit I2C and SMBus, low power I/O port with interruptFeatures2n 8-bit I C-bus GPIOn Operating power supply voltage range of 2.3 V to 5.5 Vn 5 V tolerant ..
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PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
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PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB3 ,PNP resistor-equipped double transistor R1 = 4.7 kOhm, R2 = openLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
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9534-PCA9534BS-PCA9534D
8-bit I2C and SMBus, low power I/O port with interrupt
General descriptionThe PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2 C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2 C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
The PCA9534 consists of an 8-bit Configuration register (Input or Output selection); 8-bit
Input register, 8-bit Output register andan 8-bit Polarity Inversion register (active HIGHor
active LOW operation). The system master can enable the I/Osas either inputsor outputs
by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding Input or Output register. The polarity of the Input Port register can be
inverted with the Polarity Inversion register. All registers can be read by the system
master. Although pin-to-pin and I2 C-bus address compatible with the PCF8574 series,
software changes are required dueto the enhancements and are discussedin Application
Note AN469.
The PCA9534is identicalto the PCA9554 exceptfor the removalof the internal I/O pull-up
resistor which greatly reduces power consumption when the I/Os are held LOW.
The PCA9534 open-drain interrupt outputis activated when any input state differs fromits
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2 C-bus address and allow up to eight
devices to share the same I2 C-bus/SMBus.
Features 8-bit I2 C-bus GPIO Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset
PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
Rev. 03 — 6 November 2006 Product data sheet
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt 8 I/O pins which default to 8 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offeredin four different packages: SO16, TSSOP16, and HVQFN16(4×4× 0.85 mm
and 3×3× 0.85 mm versions)
Ordering information Block diagram
Table 1. Ordering informationTamb = −40°Cto +85 °C.
PCA9534D PCA9534D SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
PCA9534PW PCA9534 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9534BS 9534 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body4×4× 0.85 mm
SOT629-1
PCA9534BS3 P34 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body3×3× 0.85 mm
SOT758-1
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description 1 15 address input 0 2 16 address input 1 3 1 address input 2
IO0 4 2 input/output 0
IO1 5 3 input/output 1
IO2 6 4 input/output 2
IO3 7 5 input/output 3
VSS 86[1] ground supply voltage
IO4 9 7 input/output 4
IO5 10 8 input/output 5
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt[1] HVQFN packagedie supply groundis connectedto both VSSpin and exposed center pad. VSSpin mustbe
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance,the exposed pad needstobe solderedtothe board usinga corresponding thermalpadonthe
board andfor proper heat conduction throughthe board, thermal vias needtobe incorporatedinthe PCBin
the thermal pad region.
Functional descriptionRefer to Figure 1 “Block diagram of PCA9534”.
6.1 Registers
6.1.1 Command byteThe command byteis the first byteto follow the address byte duringa write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port registerThis registerisa read-only port.It reflects the incoming logic levelsof the pins, regardless whether the pinis definedasan inputoran outputby Register3. Writesto this register
have no effect.
The default ‘X’ is determined by the externally applied logic level.
IO6 11 9 input/output 6
IO7 12 10 input/output 7
INT 13 11 interrupt output (open-drain)
SCL 14 12 serial clock line
SDA 15 13 serial data line
VDD 16 14 supply voltage
Table 2. Pin description …continued
Table 3. Command byte read byte Input Port register read/write byte Output Port register read/write byte Polarity Inversion register read/write byte Configuration register
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
6.1.3 Register 1 - Output Port registerThis register reflects the outgoing logic levelsof the pins definedas outputsby Register3.
Bit valuesin this register haveno effecton pins definedas inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection,
not the actual pinvalue.
6.1.4 Register 2 - Polarity Inversion registerThis register allows the user to invert the polarity of the Input Port register data. If a bit in
this registeris set (written with ‘1’), the corresponding Input Port datais inverted.Ifabitin
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 4. Register 0 - Input Port register bit description I7 read only X determined by externally applied logic level I6 read only X I5 read only X I4 read only X I3 read only X I2 read only X I1 read only X I0 read only X
Table 5. Register 1 - Output Port register bit descriptionLegend: * default value. O7 R 1* reflects outgoing logic levels of pins defined as
outputs by Register 36O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
Table 6. Register 2 - Polarity Inversion register bit descriptionLegend: * default value. N7 R/W 0* inverts polarity of Input Port register data= Input Port register data retained (default value)
1 = Input Port register data inverted N6 R/W 0* N5 R/W 0* N4 R/W 0* N3 R/W 0* N2 R/W 0* N1 R/W 0* N0 R/W 0*
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
6.1.5 Register 3 - Configuration registerThis register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pinis enabledasan input with high-impedance output driver.Ifabitin
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
6.2 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9534 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9534 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.3 Interrupt outputThe open-drain interrupt output is activated when one of the port pins change state and
the pinis configuredasan input. The interruptis deactivated when the input returnstoits
previous state or the Input Port register is read.
Note that changingan I/O from and outputtoan input may causea false interruptto occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O portWhen an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage maybe raised above VDDtoa maximumof 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
stateof the Output Port register. Care shouldbe exercisedifan external voltageis appliedan I/O configuredasan output becauseof the low-impedance paths that exist between
the pin and either VDD or VSS.
Table 7. Register 3 - Configuration register bit descriptionLegend: * default value. C7 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value) C6 R/W 1* C5 R/W 1* C4 R/W 1* C3 R/W 1* C2 R/W 1* C1 R/W 1* C0 R/W 1*
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
6.5 Device address
6.6 Bus transactionsData is transmitted to the PCA9534 registers using the Write mode as shown in Figure8
and Figure9. Datais read from the PCA9534 registers using the Read modeas shownin
Figure10 and Figure 11. These devicesdo not implementan auto-increment function,so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt Application design-in information
7.1 Minimizing IDD when the I/O us used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the IOn pins greater than or equal to VDD when the LED is
off. Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD
less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the
I/OVIator above VDD and prevents additional supply current consumption when the LED
is off.
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt Limiting values
Table 8. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V input current - ±20 mA
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(IOn) output current on pin IOn - ±50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature −40 +85 °C
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt Static characteristics
Table 9. Static characteristicsVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
SuppliesVDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD= 5.5V; load; fSCL= 100 kHz 104 175 μA
Istb standby current Standby mode; VDD= 5.5V;no load;
fSCL=0 kHz; I/O= inputs =VSS - 0.25 1 μA =VDD - 0.25 1 μA
VPOR power-on reset voltage no load; VI =VDD or VSS [1]- 1.5 1.65 V
Input SCL; input/output SDAVIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL= 0.4V 3 6 - mA leakage current VI =VDD =VSS −1- +1 μA input capacitance VI =VSS - 5 10 pF
I/OsVIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL= 0.5 V; VDD= 2.3V [2] 810 - mA
VOL= 0.7 V; VDD= 2.3V [2] 10 13 - mA
VOL= 0.5 V; VDD= 3.0V [2] 814 - mA
VOL= 0.7 V; VDD= 3.0V [2] 10 19 - mA
VOL= 0.5 V; VDD= 4.5V [2] 817 - mA
VOL= 0.7 V; VDD= 4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH=−8 mA; VDD= 2.3V [3] 1.8 - - V
IOH= −10 mA; VDD= 2.3V [3] 1.7 - - V
IOH=−8 mA; VDD= 3.0V [3] 2.6 - - V
IOH= −10 mA; VDD= 3.0V [3] 2.5 - - V
IOH=−8 mA; VDD= 4.75V [3] 4.1 - - V
IOH= −10 mA; VDD= 4.75V [3] 4.0 - - V
ILI input leakage current VI =VDD =VSS −1- +1 μA input capacitance - 5 10 pF
Interrupt INTIOL LOW-level output current VOL= 0.4V 3 - - mA
Select inputs A0, A1, A2VIL LOW-level input voltage −0.5 - 0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current −1- 1 μA
NXP Semiconductors PCA9534
8-bit I2 C-bus and SMBus low power I/O port with interrupt[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb= total capacitance of one bus line in pF.
Table 10. Dynamic characteristicsfSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition
4.7 - 1.3 - μs
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - μs
tSU;STA set-up time for a repeated START
condition
4.7 - 0.6 - μs
tSU;STO set-up time for STOP condition 4.0 - 0.6 - μs
tHD;DAT data hold time 0 - 0 - μs
tVD:ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 μs
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - μs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - μs rise time of both SDA and SCL signals - 1000 20+ 0.1Cb[3] 300 ns fall time of both SDA and SCL signals - 300 20+ 0.1Cb[3] 300 μs
tSP pulse width of spikes that must be
suppressed by the input filter 50 - 50 ns
Port timingtv(Q) data output valid time - 200 - 200 ns
tsu(D) data input setup time 100 - 100 - ns
th(D) data input hold time 1 - 1 - μs
Interrupt timingtv(INT_N) valid time on pin INT - 4 - 4 μs
trst(INT_N) reset time on pin INT - 4 - 4 μs
