SNJ54LS273J ,Octal D-type Flip-Flop With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
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7801001RA-JM38510/32501BRA-SN54LS273J .-SNJ54LS-273FK-SNJ54LS273J-SNJ54LS273W
Octal D-type Flip-Flop With Clear
CLK
CLR
logic symbol† This symbol is in accordance with ANSI/IEEE Std.
91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, J, N, and W packages.
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
descriptionThese monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear input.
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock input is at
either the high or low level, the D input signal has
no effect ar the output.
These flip-flops are guaranteed to respond to
clock frequencies ranging form 0 to 30 megahertz
while maximum clock frequency is typically 40
megahertz. Typical power dissipation is 39
milliwatts per flip-flop for the ′273 and 10 milliwatts
for the ′LS273.
FUNCTION TABLE
(each flip-flop)
SN54LS273... FK PACKAGE
(TOP VIEW)GND
CLK1QCLR
GND
CLK
