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74VHC86MFSCN/a3avaiQuad 2-Input Exclusive-OR Gate
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74VHC86M-74VHC86MTCX-74VHC86MX-74VHC86N-74VHC86SJ-74VHC86SJX
Quad 2-Input Exclusive-OR Gate
74VHC86 Quad 2-Input Exclusive-OR Gate November 1992 Revised February 2005 74VHC86 Quad 2-Input Exclusive-OR Gate General Description Features The VHC86 is an advanced high speed CMOS QuadHigh Speed: t 4.8 ns (typ) at V 5V PD CC Exclusive OR Gate fabricated with silicon gate CMOS tech- Low Power Dissipation: I 2 PA (Max.) @ T 25qC CC A nology. It achieves the high speed operation similar to High Noise Immunity: V V 28% V (Min.) equivalent Bipolar Schottky TTL while maintaining the NIH NIL CC CMOS low power dissipation.Power down protection is provided on all inputs An input protection circuit ensures that 0V to 7V can beLow Noise: V 0.8V (Max.) OLP applied to the input pins without regard to the supply volt- Pin and Function Compatible with 74HC86 age. This device can be used to interface 5V to 3V systems and on two supply systems such as battery back up. This circuit prevents device destruction due to mismatched sup- ply and input voltages. Ordering Code: Package Order Number Package Description Number 74VHC86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC86MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm (Note 1) Wide 74VHC86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions AB O LLL Pin Names Description LH H A –A Inputs 0 3 HL H B –B Inputs 0 3 HH L O –O Outputs 0 3 © 2005 DS011517
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