74VHC573M ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING74VHC573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUTS NON INVERTING■ HIGH SPEED: t = 5.0 ns (TYP.) at V =5 ..
74VHC573MTC ,Octal D-Type Latch with 3-STATE Outputs74VHC573 Octal D-Type Latch with 3-STATE OutputsMarch 1993Revised April 199974VHC573Octal D-Type La ..
74VHC573MTC ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand input voltages.The VHC573 is an advanced high speed CMOS octal latchwith 3-S ..
74VHC573MTCX ,Octal D-Type Latch with 3-STATE OutputsFunctional Description Truth TableThe VHC573 contains eight D-type latches with 3-STATEInputs Outpu ..
74VHC573MX ,Octal D-Type Latch with 3-STATE OutputsGeneral Descriptionand input voltages.The VHC573 is an advanced high speed CMOS octal latchwith 3-S ..
74VHC573MX ,Octal D-Type Latch with 3-STATE OutputsFeaturestechnology. It achieves the high speed operation similar toequivalent Bipolar Schottky TTL ..
74VHC573M-74VHC573TTR
OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING
1/11October 2002 HIGH SPEED:tPD= 5.0ns (TYP.)atVCC =5V LOW POWER DISSIPATION:
ICC =4 μA (MAX.)at TA=25°C HIGH NOISE IMMUNITY:
VNIH =VNIL= 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =8 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR)= 2Vto 5.5V PIN AND FUNCTION COMPATIBLE WITH SERIES 573 IMPROVED LATCH-UP IMMUNITY LOW NOISE:V OLP= 0.9V (MAX.)
DESCRIPTIONThe 74VHC573 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiringC2 MOS technology.
These8bit D-Type latchare controlledbya latch
enable input (LE) andan output enable input (OE).
While the LE inputsis heldata high level, theQ
outputs will follow the data input precisely. When
the LEis taken low, theQ outputs will be latched
preciselyat the logic levelofD input data. While
the (OE) inputis low, the8 outputs will beina
normal logic state (highor low logic level) and
while (OE)isin high level, the outputs willbeina
high impedance state.
Power down protectionis provided onall inputs
and0to 7V can be accepted on inputs with no
regardto the supply voltage. This device can be
usedto interface 5Vto 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC573OCTAL D-TYPE LATCH
WITH3 STATE OUTPUTS NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC5732/11
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE: Don’t Care: High Impedance:Q Outputsare Latchedatthe time whentheLE inputis takenlow logic level
LOGIC DIAGRAMThis logic diagramhasnotbe usedto estimate propagation delays
74VHC5733/11
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied
RECOMMENDED OPERATING CONDITIONSVIN from 30%to 70%of VCC
74VHC5734/11
SPECIFICATIONS
74VHC573
5/11 ELECTRICAL CHARACTERISTICS (Inputtr=tf =3ns)
(*) Voltage rangeis 3.3V± 0.3V
(**) Voltage rangeis 5.0V± 0.5V
Note1: Parameter guaranteedby design. tsoLH =|tpLHm -tpLHn|, tsoHL =|tpHLm -tpHLn|
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load.(Referto Test Circuit).Average operating currentcanbe obtainedbythe following equation.ICC(opr)=CPD xVCCxfIN+ICC/8 (per Latch)
74VHC573
6/11
DYNAMIC SWITCHING CHARACTERISTICS Worst case package. Max numberof outputs definedas(n). Data inputsare driven0Vto 5.0V, (n-1) outputs switchingand one outputat GND. Max numberof data inputs(n) switching. (n-1) switching0Vto 5.0V. Inputs undertest switching: 5.0Vto threshold (VILD),0Vto threshold
(VIHD), f=1MHz.
TEST CIRCUIT =15/50pFor equivalent (includesjig and probe capacitance) =R1=1KΩ or equivalent =ZOUTof pulse generator (typically 50Ω)
