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74VHC4040MTCFAIRCHILN/a140avai12-Stage Binary Counter
74VHC4040MTCXFAIRCN/a243avai12-Stage Binary Counter
74VHC4040MTCXFAIRCHILN/a258avai12-Stage Binary Counter
74VHC4040MXFSCN/a150avai12-Stage Binary Counter


74VHC4040MTCX ,12-Stage Binary CounterFeaturesthe high-speed operation similar to equivalent BipolarSchottky TTL while maintaining the CM ..
74VHC4040MTCX ,12-Stage Binary CounterGeneral Descriptionmatched supply and input voltages.The VHC4040 is an advanced high-speed CMOS dev ..
74VHC4040MX ,12-Stage Binary Counter74VHC4040 12-Stage Binary CounterAugust 1993Revised April 199974VHC404012-Stage Binary Counterbacku ..
74VHC4046 ,CMOS Phase Lock LoopGeneral Descriptionmonics than the other two comparators.The VHC4046 is a low power phase lock loop ..
74VHC4046M ,CMOS Phase Lock LoopBlock Diagram 274VHC404674VHC4046Absolute Maximum Ratings(Note 1) Recommended Operating (Note 2)Con ..
74VHC4046MTCX ,CMOS Phase Lock LoopGeneral Descriptionmonics than the other two comparators.The VHC4046 is a low power phase lock loop ..


74VHC4040MTC-74VHC4040MTCX-74VHC4040MX
12-Stage Binary Counter
74VHC4040 12-Stage Binary Counter August 1993 Revised April 1999 74VHC4040 12-Stage Binary Counter backup. This circuit prevents device destruction due to mis- General Description matched supply and input voltages. The VHC4040 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves Features the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi- � High speed; f = 210 MHz at V = 5V MAX CC pation. The VHC4040 is a 12-stage counter which incre- � Low power dissipation: I = 4 μA (max) at T = 25°C CC A ments on the negative edge of the input clock and all � High noise immunity: V =V = 28% V (min) NIH NIL CC outputs are reset to a low level by applying a logical high on the reset input. An input protection circuit insures that � Power down protection is provided on all inputs 0V to 7V can be applied to the inputs without regard to the � Wide operating voltage range: V (opr) = 2V − 5.5V CC supply voltage. This device can be used to interface 5V to � Low noise: V = 0.8V (max) OLP 3V systems and two supply systems such as battery � Pin and function compatible with 74HC4040 Ordering Code: Order Number Package Number Package Description 74VHC4040M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC4040MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC4040N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description Q –Q Flip-Flop Outputs 0 11 CP Negative Edged Triggered Clock MR Master Reset © 1999 DS011641.prf
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