IC Phoenix
 
Home ›  7729 > 74VHC273M-74VHC273MTCX-74VHC273MX-74VHC273N-74VHC273SJ-74VHC273SJX,Octal D-Type Flip-Flop
74VHC273M-74VHC273MTCX-74VHC273MX-74VHC273N-74VHC273SJ Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
74VHC273MFAIRCHILN/a980avaiOctal D-Type Flip-Flop
74VHC273MF ?N/a107avaiOctal D-Type Flip-Flop
74VHC273MTCXN/a2391avaiOctal D-Type Flip-Flop
74VHC273MXFAIRCHILN/a10000avaiOctal D-Type Flip-Flop
74VHC273MXFAIN/a1002avaiOctal D-Type Flip-Flop
74VHC273MXFAIRCN/a8000avaiOctal D-Type Flip-Flop
74VHC273NFUJN/a15avaiOctal D-Type Flip-Flop
74VHC273SJTOSHIBAN/a160avaiOctal D-Type Flip-Flop
74VHC273SJXFAIRCHILD 仙童N/a247avaiOctal D-Type Flip-Flop


74VHC273MX ,Octal D-Type Flip-Flop74VHC273 Octal D-Type Flip-FlopApril 1994Revised May 200374VHC273Octal D-Type Flip-Flop
74VHC273MX ,Octal D-Type Flip-FlopFeaturesThe VHC273 is an advanced high speed CMOS Octal

74VHC273M-74VHC273MTCX-74VHC273MX-74VHC273N-74VHC273SJ-74VHC273SJX
Octal D-Type Flip-Flop
74VHC273 Octal D-Type Flip-Flop April 1994 Revised May 2003 74VHC273 Octal D-Type Flip-Flop General Description Features The VHC273 is an advanced high speed CMOS OctalHigh Speed: f = 165 MHz (typ) at V = 5V MAX CC D-type flip-flop fabricated with silicon gate CMOS technol- Low power dissipation: I = 4 μA (max) at T = 25°C CC A ogy. It achieves the high speed operation similar to equiva- High noise immunity: V = V = 28% V (min) lent Bipolar Schottky TTL while maintaining the CMOS low NIH NIL CC power dissipation.Power down protection is provided on all inputs The register has a common buffered Clock (CP) which isLow noise: V = 0.9V (max) OLP fully edge-triggered. The state of each D input, one setup Pin and function compatible with 74HC273 time before the LOW-to-HIGH clock transition, is trans- Leadless DQFN Package ferred to the corresponding flip-flop’s Q output. The Master Reset (MR) input will clear all flip-flops simultaneously. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. An input protection circuit insures that 0V to 7V can be applied to the inputs pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Ordering Code: Package Order Number Package Description Number 74VHC273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC273BQ MLP020B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, (Preliminary) (Preliminary) 2.5 x 4.5mm 74VHC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 DS011670
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED