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74VHC245M-74VHC245MTR-74VHC245TTR
OCTAL BUS TRANSCEIVER (3-STATE)
1/9June 2001 HIGH SPEED: tPD = 4.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 4 μA (MAX.) at TA =25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON
CONTROL INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 245 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
DESCRIPTIONThe 74VHC245 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
This IC is intended for two-way asynchronous
communication between data busses; the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the busses are
effectively isolated.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
74VHC245OCTAL BUS
TRANSCEIVER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC2452/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don‘t Care
Z : High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS 1) VIN from 30% to 70% of VCC
74VHC2453/9
DC SPECIFICATIONS
74VHC2454/9
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
74VHC2455/9
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
TEST CIRCUIT CL =15/ 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74VHC2456/9
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
