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74VHC157M-74VHC157MTC-74VHC157MTCX-74VHC157MX-74VHC157SJ Fast Delivery,Good Price
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74VHC157MNSN/a816avaiQUAD 2 CHANNEL MULTIPLEXER
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74VHC157MTCXFAIRCHILN/a2402avaiQuad 2-Input Multiplexer
74VHC157MXNSCN/a7500avaiQuad 2-Input Multiplexer
74VHC157SJFAIN/a64avaiQuad 2-Input Multiplexer
74VHC157SJFAIRCHILN/a74avaiQuad 2-Input Multiplexer
74VHC157SJXFAIRCHILN/a2000avaiQuad 2-Input Multiplexer
74VHC157SJXN/a714avaiQuad 2-Input Multiplexer


74VHC157MX ,Quad 2-Input MultiplexerGeneral Descriptionand on two supply systems such as battery back up. ThisThe VHC157 is an advanced ..
74VHC157SJ ,Quad 2-Input MultiplexerGeneral Descriptionand on two supply systems such as battery back up. ThisThe VHC157 is an advanced ..
74VHC157SJ ,Quad 2-Input Multiplexer74VHC157 Quad 2-Input MultiplexerNovember 1992Revised April 199974VHC157Quad 2-Input Multiplexerage ..
74VHC157SJX ,Quad 2-Input MultiplexerFunctional DescriptionThe VHC157 is a quad 2-input multiplexer. It selects fourInputs Outputsbits o ..
74VHC157SJX ,Quad 2-Input MultiplexerFunctional DescriptionThe VHC157 is a quad 2-input multiplexer. It selects fourInputs Outputsbits o ..
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74VHC157M-74VHC157MTC-74VHC157MTCX-74VHC157MX-74VHC157SJ-74VHC157SJX
Quad 2-Input Multiplexer
74VHC157 Quad 2-Input Multiplexer November 1992 Revised April 1999 74VHC157 Quad 2-Input Multiplexer age. This device can be used to interface 5V to 3V systems General Description and on two supply systems such as battery back up. This The VHC157 is an advanced high speed CMOS Quad 2- circuit prevents device destruction due to mismatched sup- Channel Multiplexer fabricated with silicon gate CMOS ply and input voltages. technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the Features CMOS low power dissipation. � High Speed: t = 4.1 ns (typ) at V = 5V It consists of four 2-input digital multiplexers with common PD CC select and enable inputs. When the ENABLE input is held � Low power dissipation: I = 4 μA (max.) at T = 25°C CC A “H” level, selection of data is inhibited and all the outputs � High noise immunity: V = V = 28% V (min.) NIH NIL CC become “L” level. The SELECT decoding determines � Power down protection is provided on all inputs whether the I or I inputs get routed to their correspond- 0x 1x ing outputs. � Low noise: V = 0.8V (max.) OLP An Input protection circuit ensures that 0V to 7V can be � Pin and function compatible with 74HC157 applied to the input pins without regard to the supply volt- Ordering Code: Order Number Package Number Package Description 74VHC157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 74VHC157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC157N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description I –I Source 0 Data Inputs 0a 0d I –I Source 1 Data Inputs 1a 1d E Enable Input S Select Input Z –Z Outputs a d © 1999 DS011536.prf
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