74VHC132TTR ,QUAD 2-INPUT SCHMITT NAND GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74VHC138 ,3 TO 8 DECODER (INVERTING)74VHC1383 TO 8 LINE DECODER (INVERTING)
74VHC132TTR
QUAD 2-INPUT SCHMITT NAND GATE
1/8June 2001 HIGH SPEED: tPD = 3.9 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION:CC = 2 μA (MAX.) at TA =25°C TYPICAL HYSTERESIS : h = 1V at VCC = 4.5V
� POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS:PLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)
DESCRIPTIONThe 74VHC132 is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C2 MOS technology.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
Pin configuration and function are the same as
those of the 74VHC00 but the 74VHC132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC132QUAD 2-INPUT SCHMITT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74VHC1322/8
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
74VHC1323/8
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
74VHC1324/8
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74VHC1325/8
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
