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|74VHC123ASJX from FAI, Fairchild Semiconductor 1887pcs,Dual Retriggerable Monastable Multivibrator|
|74VHC123ASJX from FAIRCHILD, Fairchild Semiconductor 49pcs , SOP-16,Dual Retriggerable Monastable Multivibrator|
Featuresinput, either of which can be used as an inhibit input. Alsoincluded is a clear input that when taken low resets the High Speed: one-shot. The VHC123A can be triggered on the positivet = 8.1 ns (typ) at T = 25°CPD Atransition of the clear while A is held low and B is held high. Low Power Dissipation:The output pulse width is determined by the equation:I = 4 μA (Max) at T = 25°CPW = (R )(C ); where PW is in seconds, R is in ohms, and CC Ax xC is in farads. Active State: I = 600 μA (Max) at T = 25°CCC ALimits for R and C are:x x High Noise Immunity: V = V = 28% V (min)NIH NIL CCExternal capacitor, C No limitx Power down protection is provided on all inputsExternal resistors, R V = 2.0V, 5 kΩ min Pin and function compatible with 74HC123Ax CCV > 3.0V, 1 kΩ minCC Ordering Code: Order Number Package Number Package Description74VHC123AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow74VHC123ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74VHC123AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74VHC123AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WideSurface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Logic Symbol Connection DiagramIEEE/IEC 1999 Fairchild Semiconductor Corporation DS011621.prf Pin Descriptions Truth TablePin Names DescriptionInputs Outputs FunctionA Trigger Inputs (Negative Edge)A BCLR QQB Trigger Inputs (Positive Edge)
|74VHC123MTCX F |
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|74VHC123ASJX ,Dual Retriggerable Monastable MultivibratorBlock DiagramsNote A: C , R , D are external Capacitor, Resistor, and Diode, respectively.x x xNote ..|
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