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74VHC112NSCN/a2avaiDual J-K Flip-Flops with Preset and Clear


74VHC112 ,Dual J-K Flip-Flops with Preset and Clear74VHC112DualJ-KFlip-FlopswithPresetandClearSeptember199674VHC112DualJ-KFlip-FlopswithPresetandClear ..
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74VHC112MTC ,Dual J-K Flip-Flops with Preset and ClearGeneral Descriptionand Q HIGH. The VHC112 is an advanced high speed CMOS deviceAn input protection ..
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74VHC112MX ,Dual J-K Flip-Flops with Preset and ClearGeneral Descriptionand Q HIGH. The VHC112 is an advanced high speed CMOS deviceAn input protection ..
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74VHC112
Dual J-K Flip-Flops with Preset and Clear
TL/F/12123
74VHC112
Dual
J-K
Flip-Flops
with
Preset
and
Clear
September 1996
74VHC112
Dual J-K Flip-Flops with Preset and Clear
General Description
The ’VHC112isan advanced high speed CMOS devicefab-
ricated with silicon gate CMOS technology.It achievesthe
high-speed operation similarto equivalent Bipolar Schottky
TTL while maintainingthe CMOSlow power dissipation.
The VHC112 containstwo independent, high-speedJKflip-
flops with DirectSetand Clear inputs. Synchronous state
changesare initiatedbythe falling edgeofthe clock. Trig-
gering occursata voltage levelofthe clockandisnotdi-
rectly relatedto transition time. TheJ andK inputs can
change whenthe clockisin either state without affecting
the flip-flop, providedthat theyareinthe desired statedur-
ingthe recommended setupand hold times relativetothe
falling edgeofthe clock. The LOW signalonPRor CLR
prevents clocking and forcesQandQ HIGH, respectively.
Simultaneous LOW signalsonPR and CLR force bothQ
andQ HIGH. input protection circuit ensures that0Vto7Vcanbe
appliedtothe input pins without regardtothe supply volt-
age. This devicecanbe usedto interface5Vto3V systems
andtwo supply systemssuch asbattery backup. This circuit
prevents device destructiondueto mismatched supplyand
input voltages.
Features High noise immunity Power down protection Low power dissipation Low noise Balanced propagation delaysPinand function compatible with 74HC112
Commercial Package Package DescriptionNumber
74VHC112M M16A 16-LeadMoldedJEDECSOIC
74VHC112SJ M16D 16-LeadMoldedEIAJ SOIC
74VHC112MTC MTC16 16-LeadMoldedJEDECType1 TSSOP
74VHC112N N16E 16-LeadMoldedDIP
Note: Surface mount packages arealso availableonTape andReel. Specifiyby appendingthe suffixletter‘‘X’’ tothe orderingcode.
Connection Diagram
Pin Assignmentfor DIP, SOICand TSSOP
TL/F/12123–1
Pin Names Description
J1,J2,K1,K2 Data Inputs
CLK1, CLK2 Clock Pulse Inputs(Active Falling edge)
CLR1, CLR2 DirectClear Inputs(Active Low)
PR1,PR2 DirectPreset Inputs (Active Low)
Q1,Q2,Q1,Q2
C1996National SemiconductorCorporation RRD-B30M96/Printed inU.S.A. http://
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