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74VCX16821MTDFAIN/a2110avaiLow Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
74VCX16821MTDXFAIN/a799avaiLow Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs


74VCX16821MTD ,Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputsapplications with I/O compatibility up to 3.6V. CCCC

74VCX16821MTD-74VCX16821MTDX
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs March 1998 Revised October 2004 74VCX16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16821 contains twenty non-inverting D-type flip-1.4V to 3.6V V supply operation CC flops with 3-STATE outputs and is intended for bus oriented 3.6V tolerant inputs and outputs applications. t PD The 74VCX16821 is designed for low voltage (1.4V to 3.5 ns max for 3.0V to 3.6V V 3.6V) V applications with I/O compatibility up to 3.6V. CC CC Power-off high impedance inputs and outputs The 74VCX16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-Supports live insertion and withdrawal (Note 1) ing low CMOS power dissipation. Static Drive (I /I ) OH OL ±24 mA @ 3.0V V CC Uses patented noise/EMI reduction circuitry Latch-up performance exceeds 300 mA ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V through a pull-up resistor; the minimum CC value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74VCX16821MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n CLK Clock Input n D –D Inputs 0 19 O –O Outputs 0 19 © 2004 DS500130
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