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74SSTUB32868AZRHR
28-Bit to 56-Bit Registered Buffer with Address-Parity Test
1FEATURES
APPLICATIONS
DESCRIPTION
74SSTUB32868A
www.ti.com.......................................................................................................................................................... SCAS846C–JULY 2007–REVISED MARCH 2009
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST Supports LVCMOS Switching Levels on the
Chip-Select Gate-Enable, Control, and RESET
23• Memberof the Texas Instruments
InputsWidebus+™ Family Checks Parity on DIMM-Independent Data•
Pinout Optimizes DDR2 DIMM PCB Layout
Inputs•
1-to-2 Outputs Support Stacked DDR2 DIMMsChanging State and Minimizes System Power Receivers, Resets All Registers, and ForcesConsumption All Outputs Low, Except QERR•
Output Edge-Control Circuitry Minimizes
Switching Noisein an Unterminated Line Supports SSTL_18 Data Inputs •
Heavily loaded DDR2 registered DIMM Differential Clock (CLK and CLK) InputsThis 28-bit 1:2 configurable registered bufferis designedfor 1.7-Vto 1.9-V VCC operation. One device per DIMM requiredto drive upto 18 stacked SDRAM loadsor two devices per DIMM are requiredto drive upto 36
stacked SDRAM loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs,
which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error (QERR) output.
The 74SSTUB32868A operates froma differential clock (CLK and CLK). Data are registeredat the crossingof
CLK going high and CLK going low.
The 74SSTUB32868A acceptsa paritybit from the memory controlleron the paritybit (PAR_IN) input, compares with the data received on the DIMM-independent D-inputs (D1−D5, D7, D9−D12, D17−D28 whenC=0;or
D1−D12, D17−D20, D22, D24−D28 whenC=1) and indicates whethera parity error has occurred on the
open-drain QERR pin (active low). The conventionis even parity; that is, valid parityis defined as an even
numberof ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,
all DIMM-independent D-inputs must be tiedtoa known logic state.
The 74SSTUB32868A includesa parity checking function. Parity, which arrives one cycle after the data inputto
whichit applies,is checked on the PAR_IN inputof the device. Two clock cycles after the data are registered,
the corresponding QERR signalis generated.
ORDERING INFORMATION(1)
ORDERABLE PARTTA PACKAGE(2) TOP-SIDE MARKINGNUMBER-40°Cto +85°C TFBGA-ZRH Tape and Reel 74SSTUB32868AZRHR SB868A
(1) Forthe most current package and ordering information, seethe Package Option Addendumatthe endof this document,or seetheTI
websiteat www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare availableat
www.ti.com/sc/package.
