74LVX138M ,Low Voltage 1-of-8 Decoder/DemultiplexerAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVX138M ,Low Voltage 1-of-8 Decoder/Demultiplexer74LVX138 Low Voltage 1-of-8 Decoder/DemultiplexerJune 1993Revised October 200374LVX138Low Voltage 1 ..
74LVX138MTC ,Low Voltage 1-of-8 Decoder/DemultiplexerFunctional DescriptionThe LVX138 high-speed 1-of-8 decoder/demultiplexer All outputs will be HIGH u ..
74LVX138MTCX ,Low Voltage 1-of-8 Decoder/DemultiplexerFunctional DescriptionThe LVX138 high-speed 1-of-8 decoder/demultiplexer All outputs will be HIGH u ..
74LVX138MX ,Low Voltage 1-of-8 Decoder/Demultiplexerfeatures three Enable0 7using one of the active LOW Enable inputs as the datainputs, two active-LOW ..
74LVX138MX ,Low Voltage 1-of-8 Decoder/Demultiplexerfeatures three Enable0 7using one of the active LOW Enable inputs as the datainputs, two active-LOW ..
854663 , 70 MHz Low-Loss Filter
854671 , 70 MHz Low-Loss Filter
854920 , Std Low-Loss 140 MHz Bandpass Filter
854920 , Std Low-Loss 140 MHz Bandpass Filter
854923 , Std Low-Loss 140 MHz Bandpass Filter
854923 , Std Low-Loss 140 MHz Bandpass Filter
74LVX138M
LOW VOLTAGE 3 TO 8 LINE DECODER (INV.) WITH CLEAR WITH 5V TOLERANT INPUTS
1/9July 2001 HIGH SPEED :
tPD = 5.5ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL :
VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION:
ICC = 4 μA (MAX.) at TA=25°C LOW NOISE: OLP = 0.3V (TYP .) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS
DESCRIPTIONThe 74LVX138 is a low voltage CMOS 3 TO 8
LINE DECODER (INVERTING) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2 MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
If the device is enabled, 3 binary select (A, B, and
C) determine which one of the outputs will go low.
If enable input G1 is held low or either G2A or G2B
is held high, the decoding function is inhibited and
all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX138LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LVX1382/9
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
74LVX1383/9
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
DC SPECIFICATIONS
74LVX1384/9
DYNAMIC SWITCHING CHARACTERISTICS 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
74LVX1385/9
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
74LVX1386/9
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
