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74LVTH162245DGGRG4-SN74LVTH162245-SN74LVTH162245DGGR-SN74LVTH162245DL-SN74LVTH162245DLR-SN74LVTH162245KR
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN54LVTH162245..SN74LVTH162245... DGG OR DL PACKAGE
(TOP VIEW)1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION/ORDERING INFORMATION
SN54LVTH162245, SN74LVTH162245
3.3-V ABT 16-BIT BUS TRANSCEIVERS Membersof the Texas Instruments Widebus™
Family A-Port Outputs Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required Support Mixed-Mode Signal Operation
Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation 2.7V Typical VOLP (Output Ground Bounce)V VCC= 3.3V,TA= 25°C Ioff and Power-Up 3-State Support Hot
Insertion Bus Hold on Data Inputs Eliminates the
for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize
High-Speed Switching Noise Flow-Through Architecture Optimizes
Layout Latch-Up Performance Exceeds 500 mA
JESD17 ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)The 'LVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capabilitya TTL interfacetoa 5-V system
These devices can be used as two 8-bit or one 16-bit transceiver. devices allow data
transmission from theA busto theB busor theB busto theA bus, depending the logic levelat the
direction-control (DIR) input. The output-enable (OE) input can be usedto disable theso that the buses
are effectively isolated.
The logic levelsof the direction-control (DIR) and the output-enable (OE) input activate either the B-port
outputsor the A-port outputsor place both ports into the high-impedance mode. The device transmits
data from theA busto theB bus when the B-port outputs are activated, and from theBto theA bus when
the A-port outputs are activated. The input circuitryon bothA andB portsis always active must havea logic
HIGHor LOW level appliedto prevent excess and ICCZ.
Active bus-hold circuitry holds unusedor inputsata valid logic state. Use pullupor pulldown the bus-hold circuitryis not recommended. outputs, designedto sourceor sink upto12 mA, include equivalent 22-Ω series resistors and
