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74LVQ273QSC
Low Voltage Octal D Flip-Flop
74LVQ273 Low Voltage Octal D-Type Flip-Flop February 1992 Revised June 2001 74LVQ273 Low Voltage Octal D-Type Flip-Flop General Description Features The LVQ273 has eight edge-triggered D-type flip-flops withIdeal for low power/low noise 3.3V applications individual D inputs and Q outputs. The common bufferedImplements patented EMI reduction circuitry Clock (CP) and Master Reset (MR) input load and reset Available in SOIC JEDEC, SOIC EIAJ and QSOP (clear) all flip-flops simultaneously. packages The register is fully edge-triggered. The state of each D Guaranteed simultaneous switching noise level and input, one setup time before the LOW-to-HIGH clock transi- dynamic threshold performance tion, is transferred to the corresponding flip-flop’s Q output. Improved latch-up immunity All outputs will be forced LOW independently of Clock or Guaranteed incident wave switching into 75Ω Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only4 kV minimum ESD immunity is required and the Clock and Master Reset are common to all storage elements. Ordering Code: Order Number Package Number Package Description 74LVQ273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ273QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D –D Data Inputs 0 7 MR Master Reset CP Clock Pulse Input Q –Q Data Outputs 0 7 © 2001 DS011358
