74LVQ04 ,HEX INVERTERAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ04 ,HEX INVERTER
74LVQ04 ,HEX INVERTER
74LVQ04M ,HEX INVERTERapplications.74 SERIES 04 The internal circuit is composed of 3 stagesincluding buffer output, whic ..
74LVQ04MTR ,HEX INVERTERAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVQ04SCX ,Low Voltage Hex Inverter
82CNQ030SL ,30V 80A Schottky Common Cathode Diode in a D61-8-SL packageFeaturesThe 82CNQ030 center tap Schottky rectifier module has beenoptimized for very low forward vo ..
82CNQ030SM ,30V 80A Schottky Common Cathode Diode in a D61-8-SM packagePD-2.270 rev. B 01/9982CNQ030SCHOTTKY RECTIFIER 80 AmpMajor Ratings and Characteristics Descripti ..
82S100/BXA , Field Programmable Logic Array
82S131 ,2K-bit TTL bipolar PROM
83021012A ,8-Bit Universal Shift/Storage Registers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
83021AMILF , 1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR
74LVQ04
HEX INVERTER
1/11July 2004 HIGH SPEED:
tPD = 4.5ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION:
ICC = 2μA(MAX.) at TA=25°C LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: PLH ≅ t PHL OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 04 IMPROVED LATCH-UP IMMUNITY
DESCRIPTIONThe 74LVQ04 is a low voltage CMOS HEX
INVERTER fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVQ04LOW VOLTAGE CMOS HEX INVERTER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 5
74LVQ042/11
Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description
Table 3: Truth Table
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
74LVQ043/11
Table 6: DC Specifications 1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics 1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
74LVQ044/11
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per gate)
Figure 3: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LVQ045/11
Figure 4: Waveform: Propagation Delays (f=1MHz; 50% duty cycle)
