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74LVC273DPHIN/a3405avaiOctal D-type flip-flop with reset; positive-edge trigger
74LVC273PWPHILIPS ?N/a55850avaiOctal D-type flip-flop with reset; positive-edge trigger


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74LVC273D-74LVC273PW
Octal D-type flip-flop with reset; positive-edge trigger
Product specification
Supersedes data of 1996 Jun 06
IC24 Data Handbook
1998 May 20
Philips Semiconductors Product specification
74LVC273Octal D-type flip-flop with reset; positive-edge trigger
FEATURES
Wide supply voltage range of 1.2V to 3.6V Conforms to JEDEC standard 8-1A Inputs accept voltages up to 5.5V CMOS low power consumption Direct interface with TTL levels Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION

The 74LVC273 is a low-voltage Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr =tf 2.5 ns
NOTE:

1CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD  VCC2 x fi  (CL  VCC2  fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
 (CL  VCC 2  fo) = sum of the outputs.
ORDERING INFORMATION
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
74LVC273Octal D-type flip-flop with reset; positive-edge trigger
LOGIC SYMBOL
IEEE/IEC LOGIC SYMBOL
FUNCTION TABLE
= HIGH voltage level= HIGH voltage level one set-up time prior to the
HIGH-to-LOW CP transition= LOW voltage level = LOW voltage level one set-up time prior to the
HIGH-to-LOW CP transition= LOW-to-HIGH transition= Don’t care
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
74LVC273Octal D-type flip-flop with reset; positive-edge trigger
ABSOLUTE MAXIMUM RATINGS1

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTES:
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)
NOTE:
All typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74LVC273Octal D-type flip-flop with reset; positive-edge trigger
AC CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
NOTE:
These typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS

VM = 1.5V at VCC � 2.7V.
VM = 0.5 VCC at VCC � 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
Waveform 2. Master reset (MR) pulse width, the master reset to
Waveform 3. Data set-up and hold times for the data input (Dn)
Philips Semiconductors Product specification
74LVC273Octal D-type flip-flop with reset; positive-edge trigger
TEST CIRCUIT
Waveform 4. Load circuitry for switching times
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