74LVC1G17GM -74LVC1G17GV-74LVC1G17GW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC1G17GW ,Single Schmitt-trigger bufferFEATURES DESCRIPTION• Wide supply voltage range from 1.65 V to 5.5 V The 74LVC1G17 is a high-perfor ..
74LVC1G17GW ,Single Schmitt-trigger bufferLogic diagram6. Pinning information6.1 Pinning 74LVC1G1774LVC1G17n.c. 1 6 VCCn.c. 1 5 VCCA 2 5 n.c. ..
74LVC1G17SE-7 , SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17SE-7 , SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17W5-7 , SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17W5-7 , SINGLE SCHMITT-TRIGGER BUFFER
81487EIB ,【15kV ESD Protected, 1/8 Unit Load, 5V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers
8155H-2 , 2048-BIT STATIC HMOS RAM WITH I/O PORTS AND TIMER
8169 ,DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX⑩applications with commercial audio D/A converters. The output sampling frequency is fixed at 48 kHz ..
8-188275-4 , AMP Micro-Match Miniature Connector System
81C55 ,2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER
81C55 ,2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER

74LVC1G17GM -74LVC1G17GV-74LVC1G17GW
Single Schmitt trigger buffer
1. General description
The 74LVC1G17 provides a buffer function with Schmitt trigger input. It is capable of
transforming slowly changing input signals into sharply defined outputs.
The input can be driven from either 3.3Vor5 V devices. This feature allows the use of
this device in a mixed 3.3V and5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits Wide supply voltage range from 1.65Vto 5.5V High noise immunity Complies with JEDEC standard JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC =3.0V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5V Multiple package options Specified from 40 C to +85 C and from 40 C to +125C
74L VC1G17
Single Schmitt trigger buffer
Rev. 10 — 29 June 2012 Product data sheet
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74LVC1G17GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; leads; body width 1.25 mm
SOT353-1
74LVC1G17GV 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74LVC1G17GM 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 1 1.45 0.5 mm
SOT886
74LVC1G17GF 40 C to +125 C XSON6 plastic extremely thin small outline package; leads; 6 terminals; body 11 0.5 mm
SOT891
74LVC1G17GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74LVC1G17GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
74LVC1G17GX 40 C to +125C X2SON5 X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8 0.8 0.35 mm
SOT1226
Table 2. Marking codes
74LVC1G17GW VJ
74LVC1G17GV V17
74LVC1G17GM VJ
74LVC1G17GF VJ
74LVC1G17GN VJ
74LVC1G17GS VJ
74LVC1G17GX VJ
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 3. Pin description
n.c. 1 1, 5 not connected 2 2 data input
GND 3 3 ground (0 V) 4 4 data output
VCC 5 6 supply voltage
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 4. Function table[1]
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA output voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125C [3]- 250 mW
Tstg storage temperature 65 +150 C
Table 6. Recommended operating conditions
VCC supply voltage 1.65 - 5.5 V input voltage 0 - 5.5 V output voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
10. Static characteristicsTable 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Tamb = 40 C to +85 C
VOH HIGH-level output voltage VI = VT+ or VT = 100 A; VCC= 1.65 V to 5.5 V VCC 0.1- - V = 4 mA; VCC= 1.65 V 1.2 - - V = 8 mA; VCC= 2.3 V 1.9 - - V = 12 mA; VCC= 2.7 V 2.2 - - V = 24 mA; VCC= 3.0 V 2.3 - - V = 32 mA; VCC= 4.5 V 3.8 - - V
VOL LOW-level output voltage VI = VT+ or VT = 100 A; VCC= 1.65 V to 5.5 V - - 0.1 V = 4 mA; VCC =1.65 V - - 0.45 V = 8 mA; VCC= 2.3 V - - 0.3 V = 12 mA; VCC= 2.7 V - - 0.4 V = 24 mA; VCC= 3.0 V - - 0.55 V = 32 mA; VCC= 4.5 V - - 0.55 V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - 0.1 5 A
IOFF power-off leakage current VI or VO = 5.5 V; VCC =0 V - 0.1 10 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A
-0.1 10 A
ICC additional supply current VI =VCC  0.6 V; IO =0A;
VCC= 2.3Vto 5.5 V; per pin 5 500 A input capacitance - 5 - pF
Tamb = 40 C to +125 C
VOH HIGH-level output voltage VI = VT+ or VT = 100 A; VCC= 1.65 V to 5.5 V VCC 0.1- - V = 4 mA; VCC= 1.65 V 0.95 - - V = 8 mA; VCC= 2.3 V 1.7 - - V = 12 mA; VCC= 2.7 V 1.9 - - V = 24 mA; VCC= 3.0 V 2.0 - - V = 32 mA; VCC= 4.5 V 3.4 - - V
VOL LOW-level output voltage VI = VT+ or VT = 100 A; VCC= 1.65 V to 5.5 V - - 0.1 V = 4 mA; VCC =1.65 V - - 0.7 V = 8 mA; VCC= 2.3 V - - 0.45 V = 12 mA; VCC= 2.7 V - - 0.6 V = 24 mA; VCC= 3.0 V - - 0.80 V = 32 mA; VCC= 4.5 V - - 0.80 V input leakage current VI= 5.5Vor GND; VCC =0Vto 5.5V - - 100 A
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
[1] All typical values are measured at maximum VCC and Tamb = 25 C.
[1] All typical values are measured at Tamb = 25 C.
IOFF power-off leakage current VI or VO = 5.5 V; VCC =0 V - - 200 A
ICC supply current VI= 5.5Vor GND;
VCC= 1.65Vto 5.5V; IO =0A - 200 A
ICC additional supply current per pin; VI =VCC  0.6 V; IO =0A;
VCC= 2.3Vto 5.5 V 5000 A
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
Table 8. Transfer characteristics
At recommended operating conditions. Voltages are referenced to GND (ground=0V).
VT+ positive-going
threshold voltage
see Figure 8 and Figure9
VCC = 1.8 V 0.82 1.0 1.14 0.79 1.14 V
VCC = 2.3 V 1.03 1.2 1.40 1.00 1.40 V
VCC = 3.0 V 1.29 1.5 1.71 1.26 1.71 V
VCC = 4.5 V 1.84 2.1 2.36 1.81 2.36 V
VCC = 5.5 V 2.19 2.5 2.79 2.16 2.79 V
VT negative-going
threshold voltage
see Figure 8 and Figure9
VCC = 1.8 V 0.46 0.6 0.75 0.46 0.78 V
VCC = 2.3 V 0.65 0.8 0.96 0.65 0.99 V
VCC = 3.0 V 0.88 1.0 1.24 0.88 1.27 V
VCC = 4.5 V 1.32 1.5 1.84 1.32 1.87 V
VCC = 5.5 V 1.58 1.8 2.24 1.58 2.27 V hysteresis
voltage
see Figure 8, Figure 9 and
Figure10
VCC = 1.8 V 0.26 0.4 0.51 0.19 0.51 V
VCC = 2.3 V 0.28 0.4 0.57 0.22 0.57 V
VCC = 3.0 V 0.31 0.5 0.64 0.25 0.64 V
VCC = 4.5 V 0.40 0.6 0.77 0.34 0.77 V
VCC = 5.5 V 0.47 0.6 0.88 0.41 0.88 V
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
10.1 Transfer characteristic waveforms
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
12. Waveforms
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 12.
tpd propagation delay A to Y; see Figure11 [2]
VCC = 1.65 V to 1.95 V 1.0 4.1 11.0 1.0 14.0 ns
VCC = 2.3 V to 2.7 V 0.7 2.8 6.5 0.7 8.5 ns
VCC = 2.7 V 0.7 3.2 6.5 0.7 8.5 ns
VCC = 3.0 V to 3.6 V 0.7 3.0 5.5 0.7 7.0 ns
VCC = 4.5 V to 5.5 V 0.7 2.2 5.0 0.7 6.5 ns
CPD power dissipation
capacitance
VI = GND to VCC;
VCC= 3.3 V
[3] - 16.6 --- pF
Table 10. Measurement points
1.65 V to 1.95V 0.5 VCC 0.5 VCC
2.3 V to 2.7V 0.5 VCC 0.5 VCC
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
13. Application information
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5V 0.5 VCC 0.5 VCC
Table 10. Measurement points …continued
Table 11. Test data
1.65 V to 1.95V VCC  2.0ns 30pF 1k open
2.3 V to 2.7V VCC  2.0ns 30pF 500 open
2.7V 2.7V  2.5ns 50pF 500 open
3.0V to 3.6V 2.7V  2.5ns 50pF 500 open
4.5 V to 5.5V VCC  2.5ns 50pF 500 open
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
NXP Semiconductors 74LVC1G17
Single Schmitt trigger buffer
14. Package outline

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G17GM	NXP	N/a	5000	avai	Single Schmitt trigger buffer
74LVC1G17GV	NXP	N/a	35950	avai	Single Schmitt-trigger buffer
74LVC1G17GW	NXP	N/a	52500	avai	Single Schmitt-trigger buffer