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74LVC16373ADL
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
1. General descriptionThe 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches featuring
separate D-type inputs with bus hold (74LVCH16373A only) for each latch and 3-state
outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable
(OE) are provided for each octal. Inputs can be driven from either 3.3 V or5 V devices.
When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of
these devices in mixed 3.3 V and5 V applications.
The device consists of two sections of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the
latches are transparent, that is, the latch outputs change each time its corresponding
D-input changes. The latches store the information that was present at the D-inputs one
set-up time (tsu) preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs. When OE is HIGH, the outputs
go to the high impedance OFF-state. Operation of the OE input does not affect the state of
the latches. Bus hold on the data inputs eliminates the need for external pull-up resistors
to hold unused inputs.
2. Features and benefits5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16373A only) High-impedance when VCC =0V Complies with JEDEC standard: JESD8-7A (1.65Vto 1.95V) JESD8-5A (2.3Vto 2.7V) JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 C to +85 C and 40 C to +125C
74L VC16373A; 74LVCH16373A
16-bit D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 8 — 6 January 2014 Product data sheet
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information74LVC16373ADGG 40 Cto +125C TSSOP48 plastic thin shrink small outline package; leads; body width 6.1 mm
SOT362-1
74LVCH16373ADGG
74LVC16373ADL 40 Cto +125C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVCH16373ADL
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateNXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description1OE 1 output enable input (active LOW)
2OE 24 output enable input (active LOW)
1LE 48 latch enable input (active HIGH)
2LE 25 latch enable input (active HIGH)
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0V)
VCC 7, 18, 31, 42 supply voltage
1Q[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output
2Q[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data output
1D[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input
2D[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description[1] H= HIGH voltage level= HIGH voltage level one set-up time prior to the HIGH to LOW LE transition= LOW voltage level= LOW voltage level one set-up time prior to the HIGH to LOW LE transition= high-impedance OFF-state
7. Limiting values[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function tablePer section of eight bits [1]
Enable and read register
(transparent mode) L LL H H H
Latch and read register L L l L L
LLh H H
Latch register and disable outputs H L l L Z h HZ
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground=0V).
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI <0 50 - mA input voltage [1] 0.5 +6.5 V
IOK output clamping current VO >VCC or VO <0 - 50 mA output voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V output current VO =0V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [3]- 500 mW
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditionsVCC supply voltage 1.65 - 3.6 V
functional 1.2 - 3.6 V input voltage 0 - 5.5 V output voltage output HIGH or LOW state 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC= 1.65V to2.7V 0 - 20 ns/V
VCC= 2.7Vto 3.6V 0 - 10 ns/V
Table 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCCV
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage =VIHorVIL= 100 A;
VCC =1.65Vto3.6V
VCC 0.2 - - VCC 0.3 - V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage =VIHorVIL= 100 A;
VCC= 1.65Vto 3.6 V - 0.2 - 0.3 V =4mA; VCC = 1.65 V - - 0.45 - 0.65 V =8mA; VCC = 2.3V - - 0.6 - 0.8 V =12mA; VCC = 2.7 V - - 0.4 - 0.6 V =24mA; VCC = 3.0 V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; =5.5V orGND[2] - 0.1 5- 20 A
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
[2] The bus hold circuit is switched off when VI >VCC allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16373A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
IOZ OFF-state
output
current =VIHor VIL; VCC= 3.6 V; =5.5V orGND[2] - 0.1 5- 20 A
IOFF power-off
leakage
current
VCC = 0 V; VIorVO = 5.5V - 0.1 10 - 20 A
ICC supply
current
VCC = 3.6 V; VI =VCCor GND; =0A
-0.1 20 - 80 A
ICC additional
supply
current
per input pin;
VCC= 2.7Vto 3.6V; =VCC 0.6 V; IO =0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6V; =GNDto VCC
-5.0 - - - pF
IBHL bus hold
LOW current
VCC = 1.65; VI = 0.58 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
IBHH bus hold
HIGH current
VCC = 1.65; VI = 1.07 V [3][4] 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold
LOW
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold
HIGH
overdrive
current
VCC = 1.95 V [3][5] 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continuedAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
10. Dynamic characteristicsTable 7. Dynamic characteristicsVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
tpd propagation
delay
Dn to Qn; see Figure6 [2]
VCC = 1.2 V - 12 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.4 11.4 1.5 13.2 ns
VCC = 2.3 V to 2.7 V 1.0 2.9 5.7 1.0 6.6 ns
VCC = 2.7V 1.5 2.9 4.9 1.5 6.5 ns
VCC = 3.0 V to 3.6V 1.0 2.4 4.4 1.0 5.5 nsto Qn; see Figure7
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 2.0 6.4 12.4 2.0 14.4 ns
VCC = 2.3 V to 2.7 V 1.5 3.4 6.1 1.5 7.1 ns
VCC = 2.7V 1.5 3.0 5.3 1.5 7.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 4.8 1.5 6.0 ns
ten enable time OEto Qn; see Figure8 [2]
VCC = 1.2 V - 18 - - - ns
VCC = 1.65 V to 1.95 V 1.5 5.5 12.4 1.5 14.3 ns
VCC = 2.3 V to 2.7 V 1.0 3.1 6.6 1.0 7.6 ns
VCC = 2.7V 1.5 3.3 5.7 1.5 7.5 ns
VCC = 3.0 V to 3.6V 1.0 2.5 4.9 1.0 6.5 ns
tdis disable time OEto Qn; see Figure8 [2]
VCC = 1.2 V - 11 - - - ns
VCC = 1.65 V to 1.95 V 2.8 4.5 9.1 2.8 10.5 ns
VCC = 2.3 V to 2.7 V 1.0 2.5 5.1 1.0 6.0 ns
VCC = 2.7V 1.5 3.3 6.3 1.5 8.0 ns
VCC = 3.0 V to 3.6V 1.5 3.1 5.4 1.5 7.0 ns pulse width LE HIGH; see Figure7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6V 3.0 2.0 - 3.0 - ns
tsu set-up time Dn to LE; see Figure9
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7V 2.0 - - 2.0 - ns
VCC = 3.0 V to 3.6V 2.0 1.0 - 2.0 - ns
NXP Semiconductors 74L VC16373A; 74L VCH16373A
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs
11. Waveforms hold time Dn to LE; see Figure9
VCC = 1.65 V to 1.95 V 2.5 - - 2.5 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7V 0.9 - - 0.9 - ns
VCC = 3.0 V to 3.6V +0.9 1.0 - +0.9 - ns
tsk(o) output skew
time
VCC = 3.0 V to 3.6V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per input; VI =GNDto VCC [4]
VCC = 1.65 V to 1.95 V - 10.8 - - - pF
VCC = 2.3 V to 2.7 V - 13.0 - - - pF
VCC = 3.0 V to 3.6 V - 15.0 - - - pF
Table 7. Dynamic characteristics …continuedVoltages are referenced to GND (ground=0 V). For test circuit see Figure 10.
