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74LV595D
8-bit serial-in/serial-out or parallel-out shift register; 3-state
General descriptionThe 74LV595isan8 stage serial shift register witha storage register and 3-state outputs.
Both the shift and storage register have separate clocks.Itisa low-voltage Si-gate CMOS
device and is pin and functionally compatible with the 74HC595 and 74HCT595.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading the
device.Itis also provided withan asynchronous reset input MR (active LOW)forall8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
Features Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25°C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb =25°C Specified from −40 °Cto+85 °C and from −40°Cto +125°C Has a shift register with direct clear Multiple package options Output capability: Parallel outputs; bus driver serial output; standard ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V
Applications Serial-to-parallel data conversion Remote control holding register
74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 03 — 21 April 2009 Product data sheet
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state Ordering information Functional diagram
Table 1. Ordering information74LV595N −40°Cto +125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV595D −40°Cto +125°C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74LV595DB −40°Cto +125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74LV595PW −40°Cto +125°C TSSOP16 plastic thin shrink small outline package;16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionQ0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input 13 output enable input (active LOW) 14 serial data input
VCC 16 supply voltage
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state Functional description[1]H= HIGH voltage state; L= LOW voltage state;↑= LOW-to-HIGH transition; X= don’t care; NC= no change;= high-impedance OFF-state.
Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1] X L L X L NC a LOW-state on MR only affects the shift register ↑ L L X L L empty shift register loaded into storage register X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S). ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +4.6 V
IIK input clamping current VI< −0.5 V or VI > +0.5 V - ±20 mA
IOK output clamping current VI< −0.5 V or VI > +0.5 V - ±50 mA output current −0.5 V < VO
standard driver outputs 25 mA
bus driver outputs 35 mA
ICC supply current standard driver outputs 50 mA
bus driver outputs 70 mA
IGND ground current standard driver outputs −50 mA
bus driver outputs −70 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40°Cto +125°C [2]
DIP16 - 750 mW
SO16, SSOP16, TSSOP16 - 500 mW
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 1.0 3.3 3.6 V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature −40 - +125 °C
Δt/ΔV input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VIH HIGH-level
input voltage
VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage
VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output voltage
all outputs; VI =VIHor VIL;= −100 μA;
VCC= 1.2V - 1.2 - - - V
VCC = 2.0 V 1.8 2.0 - 1.8 - V
VCC= 2.7V 2.5 2.7 - 2.5 - V
VCC = 3.0 V 2.8 3.0 - 2.8 - V
standard outputs; =VIHor VIL; IO=−6 mA;
VCC = 3.0 V
2.4 2.82 - 2.2 - V
bus outputs; VI =VIHor VIL;=−8 mA;
VCC = 3.0 V
2.4 2.82 - 2.2 - V
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25°C.
VOL LOW-level
output voltage
all outputs; VI =VIHor VIL;= 100 μA;
VCC= 1.2 V - 0 - - - V
VCC = 2.0 V - 0 0.2 - 0.2 V
VCC = 2.7 V - 0 0.2 - 0.2 V
VCC = 3.0 V - 0 0.2 - 0.2 V
standard driver outputs
VCC= 3.0 V; IO =6mA 0.25 0.4 - 0.5 V
bus driver outputs
VCC= 3.0 V; IO =8mA 0.20 0.4 - 0.5 V input leakage
current
VCC = 3.6 V;= 5.5Vor GND - 1.0 - 1.0 μA
IOZ OFF-state
output current =VIHor VIL; =VCCor GND;
VCC= 3.6V -5- 10 μA
ICC supply current VCC = 3.6 V; =VCCor GND; IO =0A - 20 - 160 μA
ΔICC additional supply
current
per input pin;
VCC= 2.7Vto 3.6V; =VCC− 0.6V - 500 - 850 μA input capacitance - 3.5 - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 13.
tpd propagation delay SHCPto Q7S; see Figure8 [2]
VCC= 1.2V - 95 - - - ns
VCC= 2.0 V - 32 61 - 75 ns
VCC= 2.7V - 24 45 - 55 ns
VCC= 3.3 V; CL = 15 pF - 15 - - - ns
VCC= 3.0Vto 3.6V [3] - 18 36 - 44 ns
STCPto Qn; see Figure9 [2]
VCC= 1.2V - 100 - - - ns
VCC= 2.0 V - 34 65 - 77 ns
VCC= 2.7V - 25 48 - 56 ns
VCC= 3.3 V; CL = 15 pF - 16 - - - ns
VCC= 3.0Vto 3.6V [3] - 19 38 - 45 nsto Q7S; see Figure11
VCC= 1.2V - 85 - - - ns
VCC= 2.0 V - 29 56 - 66 ns
VCC= 2.7V - 21 41 - 49 ns
VCC= 3.3 V; CL = 15 pF - 14 - - - ns
VCC= 3.0Vto 3.6V [3] - 16 33 - 33 ns
ten enable time OEto Qn; see Figure12 [4]
VCC= 1.2V - 85 - - - ns
VCC= 2.0 V - 29 56 - 66 ns
VCC= 2.7V - 21 41 - 49 ns
VCC= 3.0Vto 3.6V - 16 33 - 39 ns
tdis disable time OEto Qn; see Figure12 [5]
VCC= 1.2V - 65 - - - ns
VCC= 2.0 V - 24 40 - 49 ns
VCC= 2.7V - 18 32 - 37 ns
VCC= 3.0Vto 3.6V [3] - 14 26 - 30 ns
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state pulse width SHCP, HIGH or LOW;
see Figure8
VCC= 2.0 V 34 10 - 41 - ns
VCC= 2.7V 25 8 - 30 - ns
VCC= 3.0Vto 3.6V [3] 20 6 - 24 - ns
STCP, HIGH or LOW;
see Figure9
VCC= 2.0 V 34 7 - 41 - ns
VCC= 2.7V 25 5 - 30 - ns
VCC= 3.0Vto 3.6V [3] 20 4 - 24 - ns LOW; see Figure11
VCC= 2.0 V 34 10 - 41 - ns
VCC= 2.7V 25 8 - 30 - ns
VCC= 3.0Vto 3.6V [3] 20 6 - 24 - ns
tsu set-up time DS to SHCP; see Figure10
VCC= 1.2 V - 40 - - - ns
VCC= 2.0 V 26 14 - 31 - ns
VCC= 2.7V 19 10 - 23 - ns
VCC= 3.0Vto 3.6V [3] 15 8 - 18 - ns
SHCP to STCP; see Figure9
VCC= 1.2 V - 40 - - - ns
VCC= 2.0 V 26 14 - 31 - ns
VCC= 2.7V 19 10 - 23 - ns
VCC= 3.0Vto 3.6V [3] 15 8 - 18 - ns hold time DS to SHCP; see Figure10
VCC= 1.2 V - −10.0 - - - ns
VCC= 2.0 V 5.0 −4.0 - 5.0 - ns
VCC= 2.7V 5.0 −3.0 - 5.0 - ns
VCC= 3.0Vto 3.6V 5.0 −2.0 - 5.0 - ns
trec recovery time MR to SHCP; see Figure11
VCC= 1.2 V - −35 - - - ns
VCC= 2.0 V 5.0 −12.0 - 5.0 - ns
VCC= 2.7V 5.0 −9.0 - 5.0 - ns
VCC= 3.0Vto 3.6V [3] 5.0 −7.0 - 5.0 - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 13.
NXP Semiconductors 74L V595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
[1] Typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
[6] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[7] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ ∑(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance inpF;
VCC= supply voltage in V;= number of inputs switching;
∑(CL× VCC2×fo)= sum of outputs.
12. Waveforms
fmax maximum
frequency
SHCPor STCP; see Figure8
and Figure9
VCC= 2.0 V 14.0 40.0 - 12 - MHz
VCC= 2.7V 19.0 58.0 - 16 - MHz
VCC= 3.3 V; CL = 15 pF - 77 - - - MHz
VCC= 3.0Vto 3.6V [3] 24.0 70.0 - 20 - MHz
CPD power dissipation
capacitance
VI = GND to VCC; VCC = 3.0V [7] - 115 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V). For test circuit see Figure 13.
