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74LV377PW
Octal D-type flip-flop with data enable; positive edge-trigger
Product specification
Supersedes data of 1997 Mar 04
IC24 Data Handbook
1998 Jun 10
Philips Semiconductors Product specification
74LV377Octal D-type flip-flop with data enable;
positive edge-trigger
FEATURES Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V,
Tamb = 25°C Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V,
Tamb = 25°C Ideal for addressable register applications Data enable for address and data synchronization applications Eight positive-edge triggered D-type flip-flops Output capability: standard ICC category: MSI
DESCRIPTIONThe 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Qn) of
the flip-flop. The E input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf 2.5 ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW)
PD = CPD VCC 2 fi (CL VCC 2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC 2 fo) = sum of the outputs. The condition is VI = GND to VCC
ORDERING INFORMATION
PIN DESCRIPTION
FUNCTION TABLE = HIGH voltage level = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition = LOW–to–HIGH CP transition
Philips Semiconductors Product specification
74LV377Octal D-type flip-flop with data enable;
positive edge-trigger
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
Philips Semiconductors Product specification
74LV377Octal D-type flip-flop with data enable;
positive edge-trigger
RECOMMENDED OPERATING CONDITIONS
NOTE: The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV377Octal D-type flip-flop with data enable;
positive edge-trigger
DC CHARACTERISTICS FOR THE LV FAMILYOver recommended operating conditions. Voltages are referenced to GND (ground = 0V).
NOTE: All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV377Octal D-type flip-flop with data enable;
positive edge-trigger
AC CHARACTERISTICSGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL =�K�
NOTES: Unless otherwise stated, all typical values are at Tamb = 25°C. Typical value measured at VCC = 3.3V.
