74LV164BQ Fast Delivery |IC PHOENIX CO.,LIMITED

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74LV164BQ
8-bit serial-in/parallel-out shift register
General descriptionThe 74LV164 is a low-voltage, Si-gate CMOS device and is pin and function compatible
with the 74HC164 and 74HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output
from each of the eight stages. Data is entered serially through one of two inputs (DSA or
DSB) and either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into Q0, which is the logical AND-function of the two data inputs (DSA and
DSB) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW. Features Wide operating voltage: 1.0 V to 5.5V Optimized for low-voltage applications: 1.0 V to 3.6V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6V Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25°C Typical VOHV (output VOH undershoot): >2 V at VCC = 3.3 V and Tamb = 25°C Gated serial data inputs Asynchronous master reset ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. Speciﬁed from −40 °Cto+80 °C and from −40°Cto +125 °C. Quick reference data
74L V164
8-bit serial-in/parallel-out shift register
Table 1: Quick reference data
GND=0 V; Tamb =25 °C; tr =tf≤ 2.5 ns.
tPHL,
tPLH
propagation delay VCC= 3.3 V; CL =15pF
CP to Qn - 12 - ns
MR to Qn - 12 - ns
Philips Semiconductors 74L V164
[1] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2× fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[2] The condition is VI= GND to VCC. Ordering information
fmax maximum clock
frequency
VCC= 3.3 V; CL=15pF - 78 - MHz input capacitance - 3.5 - pF
CPD power dissipation
capacitance per gate
VCC= 3.3V [1][2] -40 - pF
Table 1: Quick reference data …continued
GND=0 V; Tamb =25 °C; tr =tf≤ 2.5 ns.
Table 2: Ordering information
74LV164N −40°Cto +125°C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV164D −40°Cto +125°C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV164DB −40°Cto +125°C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV164PW −40°Cto +125°C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV164BQ −40°Cto +125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad ﬂat package; no leads; 14 terminals;
body 2.5×3× 0.85 mm
SOT762-1
Philips Semiconductors 74L V164 Functional diagram
Philips Semiconductors 74L V164 Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin description
DSA 1 data input SA
DSB 2 data input SB 3 output 0 4 output 1 5 output 2 6 output 3
GND 7 ground (0V) 8 clock input (edge triggered LOW-to-HIGH) 9 master reset input (active LOW) 10 output 4 11 output 5 12 output 6 13 output 7
VCC 14 supply voltage
Philips Semiconductors 74L V164 Functional description
7.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP
transition. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] DIP14 package: Ptot derates linearly with 12 mW/K above 70°C.
[3] SO14 package: Ptot derates linearly with 8 mW/K above 70°C.
(T)SSOP14 package: Ptot derates linearly with 5.5 mW/K above 60°C.
DHVQFN14 package: Ptot derates linearly with 4.5 mW/K above 60°C.
Table 4: Function table[1]
Reset (clear) L X X X L L to L
Shift H ↑ l l L q0 to q6 ↑ l h L q0 to q6 ↑ h l L q0 to q6 ↑ h h H q0 to q6
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0V).
VCC supply voltage −0.5 +7.0 V
IIK input diode current VI< −0.5 V or VI > VCC + 0.5V - ±20 mA
IOK output diode current VO< −0.5 V or VO > VCC + 0.5V - ±50 mA output source or sink
current= −0.5 V to (VCC + 0.5V) [1]- ±25 mA
ICC,
IGND
VCC or GND current - ±50 mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb= −40 °C to +125°C
DIP14 package [2]- 750 mW
SO14, (T)SSOP14
and DHVQFN14
packages
[3]- 500 mW
Philips Semiconductors 74L V164 Recommended operating conditions
[1] The static characteristicsare guaranteed from VCC=1.2Vto VCC=5.5V,butLV devicesare guaranteedto
function down to VCC = 1.0 V (with input levels GND or VCC).
10. Static characteristics
Table 6: Recommended operating conditions
VCC supply voltage [1] 1.0 3.3 5.5 V input voltage 0 - VCC V output voltage 0 - VCC V
Tamb ambient temperature in free air −40 - +125 °C
tr, tf input rise and fall times VCC= 1.0 V to 2.0V - - 500 ns/V
VCC= 2.0 V to 2.7V - - 200 ns/V
VCC= 2.7 V to 3.6V - - 100 ns/V
VCC= 3.6 V to 5.5V - - 50 ns/V
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = −40 °C to +85°C[1]
VIH HIGH-level input voltage VCC = 1.2V 0.9 - - V
VCC = 2.0V 1.4 - - V
VCC = 2.7 V to 3.6V 2.0 - - V
VCC = 4.5 V to 5.5V 0.7× VCC -- V
VIL LOW-level input voltage VCC = 1.2V - - 0.3 V
VCC = 2.0V - - 0.6 V
VCC = 2.7 V to 3.6V - - 0.8 V
VCC = 4.5 V to 5.5V - - 0.3× VCCV
VOH HIGH-level output voltage VI = VIH or VIL
lO = −100 μA; VCC = 1.2V - 1.2 - V
lO = −100 μA; VCC = 2.0V 1.8 2.0 - V
lO = −100 μA; VCC = 2.7V 2.5 2.7 - V
lO = −100 μA; VCC = 3.0V 2.8 3.0 - V
lO = −6 mA; VCC = 3.0V 2.40 2.82 - V
lO = −100 μA; VCC = 4.5V 4.3 4.5 - V
lO = −12 mA; VCC = 4.5V 3.60 4.20 - V
Philips Semiconductors 74L V164
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.2V - 0 - V
IO = 100 μA; VCC = 2.0V - 0 0.2 V
IO = 100 μA; VCC = 2.7V - 0 0.2 V
IO = 100 μA; VCC = 3.0V - 0 0.2 V
IO = 6 mA; VCC = 3.0V - 0.25 0.40 V
IO = 100 μA; VCC = 4.5V - 0 0.2 V
IO = 12 mA; VCC = 4.5V - 0.35 0.55 V
ILI input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 μA
ICC quiescent supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V - 20.0 μA
ΔICC additional quiescent supply
current per input
VI = VCC − 0.6 V; VCC= 2.7V 3.6V - 500 μA input capacitance - 3.5 - pF
Tamb = −40 °C to +125°C
VIH HIGH-level input voltage VCC = 1.2V 0.9 - - V
VCC = 2.0V 1.4 - - V
VCC = 2.7 V to 3.6V 2.0 - - V
VCC = 4.5 V to 5.5V 0.7× VCC -- V
VIL LOW-level input voltage VCC = 1.2V - - 0.3 V
VCC = 2.0V - - 0.6 V
VCC = 2.7 V to 3.6V - - 0.8 V
VCC = 4.5 V to 5.5V - - 0.3× VCCV
VOH HIGH-level output voltage VI = VIH or VIL
lO = −100 μA; VCC = 1.2V - - - V
lO = −100 μA; VCC = 2.0V 1.8 - - V
lO = −100 μA; VCC = 2.7V 2.5 - - V
lO = −100 μA; VCC = 3.0V 2.8 - - V
lO = −6 mA; VCC = 3.0V 2.20 - - V
lO = −100 μA; VCC = 4.5V 4.3 - - V
lO = −12 mA; VCC = 4.5V 3.50 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.2V - - - V
IO = 100 μA; VCC = 2.0V - - 0.2 V
IO = 100 μA; VCC = 2.7V - - 0.2 V
IO = 100 μA; VCC = 3.0V - - 0.2 V
IO = 6 mA; VCC = 3.0V - - 0.50 V
IO = 100 μA; VCC = 4.5V - - 0.2 V
IO = 12 mA; VCC = 4.5V - - 0.65 V
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74L V164
[1] All typical values are measured at Tamb = 25°C.
11. Dynamic characteristics
ILI input leakage current VI = VCC or GND; VCC = 5.5V - - 1.0 μA
ICC quiescent supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V - 160 μA
ΔICC additional quiescent supply
current per input
VI = VCC − 0.6 V; VCC= 2.7V 3.6V - 850 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 8: Dynamic characteristics
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure9.
Tamb = −40 °C to +85°C[1]
tPHL,
tPLH
propagation delay CP to Qn see Figure6
VCC = 1.2V - 75 - ns
VCC = 2.0V - 26 39 ns
VCC = 2.7V - 19 29 ns
VCC = 3.0 V to 3.6V - 14 23 ns
VCC = 4.5 V to 5.5V - 12 19 ns
VCC = 3.3 V; CL =15pF - 12 - ns
tPHL propagation delay MR to Qn see Figure7
VCC = 1.2V - 75 - ns
VCC = 2.0V - 26 39 ns
VCC = 2.7V - 19 29 ns
VCC = 3.0 V to 3.6V - 14 23 ns
VCC = 4.5 V to 5.5V - 12 19 ns
VCC = 3.3 V; CL =15pF - 12 - ns pulse width CP see Figure6
VCC = 2.0V 34 9 - ns
VCC = 2.7V 25 6 - ns
VCC = 3.0 V to 3.6V 20 5 - ns
VCC = 4.5 V to 5.5V 13 4 - ns pulse width MR see Figure7
VCC = 2.0V 34 10 - ns
VCC = 2.7V 25 8 - ns
VCC = 3.0 V to 3.6V 20 6 - ns
VCC = 4.5 V to 5.5V 13 5 - ns
Philips Semiconductors 74L V164
trem removal time MR to CP see Figure7
VCC = 1.2V - 30 - ns
VCC = 2.0V 19 10 - ns
VCC = 2.7V 14 8 - ns
VCC = 3.0 V to 3.6V 11 6 - ns
VCC = 4.5 V to 5.5V 8 5 - ns
tsu set-up time Dn to CP see Figure8
VCC = 1.2V - 15 - ns
VCC = 2.0V 22 5 - ns
VCC = 2.7V 16 4 - ns
VCC = 3.0 V to 3.6V 13 3 - ns
VCC = 4.5 V to 5.5V 9 2 - ns hold time Dn to CP see Figure8
VCC = 1.2V - −10 - ns
VCC = 2.0V 5 −3- ns
VCC = 2.7V 5 −2- ns
VCC = 3.0 V to 3.6V 5 −2- ns
VCC = 4.5 V to 5.5V 5 −1- ns
fmax maximum clock frequency see Figure6
VCC = 2.0V 14 40 - MHz
VCC = 2.7V 19 58 - MHz
VCC = 3.0 V to 3.6V 24 70 - MHz
VCC = 4.5 V to 5.5V 36 100 - MHz
VCC= 3.3 V; CL=15pF - 78 - MHz
CPD power dissipation capacitance
per gate
VCC= 3.3V [2][3] -40 - pF
Tamb = −40 °C to +125°C
tPHL,
tPLH
propagation delay CP to Qn see Figure6
VCC = 1.2V ---ns
VCC = 2.0V - - 49 ns
VCC = 2.7V - - 36 ns
VCC = 3.0 V to 3.6V - - 29 ns
VCC = 4.5 V to 5.5V - - 24 ns
tPHL propagation delay MR to Qn see Figure7
VCC = 1.2V ---ns
VCC = 2.0V - - 49 ns
VCC = 2.7V - - 36 ns
VCC = 3.0 V to 3.6V - - 29 ns
VCC = 4.5 V to 5.5V - - 24 ns
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure9.
Philips Semiconductors 74L V164
[1] Typical values are measured at nominal VCC and Tamb = 25°C. pulse width CP see Figure6
VCC = 2.0V 41 - - ns
VCC = 2.7V 30 - - ns
VCC = 3.0 V to 3.6V 24 - - ns
VCC = 4.5 V to 5.5V 16 - - ns pulse width MR see Figure7
VCC = 2.0V 41 - - ns
VCC = 2.7V 30 - - ns
VCC = 3.0 V to 3.6V 24 - - ns
VCC = 4.5 V to 5.5V 16 - - ns
trem removal time MR to CP see Figure7
VCC = 1.2V ---ns
VCC = 2.0V 24 - - ns
VCC = 2.7V 18 - - ns
VCC = 3.0 V to 3.6V 14 - - ns
VCC = 4.5 V to 5.5V 10 - - ns
tsu set-up time Dn to CP see Figure8
VCC = 1.2V ---ns
VCC = 2.0V 26 - - ns
VCC = 2.7V 19 - - ns
VCC = 3.0 V to 3.6V 15 - - ns
VCC = 4.5 V to 5.5V 10 - - ns hold time Dn to CP see Figure8
VCC = 1.2V ---ns
VCC = 2.0V 5 - - ns
VCC = 2.7V 5 - - ns
VCC = 3.0 V to 3.6V 5 - - ns
VCC = 4.5 V to 5.5V 5 - - ns
fmax maximum clock frequency see Figure6
VCC = 2.0V 12 - - MHz
VCC = 2.7V 16 - - MHz
VCC = 3.0 V to 3.6V 20 - - MHz
VCC = 4.5 V to 5.5V 30 - - MHz
Table 8: Dynamic characteristics …continued
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ; for test circuit see Figure9.
Philips Semiconductors 74L V164
[2] CPDis used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2× fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[3] The condition is VI= GND to VCC.
12. Waveforms

Partno	Mfg	Dc	Qty	Available	Descript
74LV164BQ	NXP	N/a	1190	avai	8-bit serial-in/parallel-out shift register