74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS90 ,Decade and Binary CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS921 14CP CP1 02 13NCNCJ Q J Q J Q J Q143 12NC Q0CPC ..
74LS90 ,Decade and Binary Counters
74LS90 ,Decade and Binary CountersSN54/74LS90SN54/74LS92DECADE COUNTER;SN54/74LS93DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTERDECADE ..
74LS92 ,Divide-by-Twelve CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS931 14CP CP1 0J Q J Q J Q J Q2 13NC14 MR1CP0CP CP C ..
7MBI40N-120 ,IGBT(1200V/40A)IGBT MODULE ( N series )n n n n Outline Drawing• • • • • • Overcurrent Limiting Function( 4 ~ 5 Tim ..
7MBP100RA060 ,Intelligent Power Module
7MBP100RA120 ,IGBT-IPM(1200V/100A)
7MBP150RA060 ,Intelligent Power Module
7MBP150RA120 ,IGBT-IPM(1200V/150A)
7MBP25RA120 ,IGBT-IPM(1200V/25A)
74LS76
LOW POWER SCHOTTKY
-----The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and
Direct Clear inputs. These dual flip-flops are designed so that when
the clock goes HIGH, the inputs are enabled and data will be accepted.
The Logic Level of the J and K inputs will perform according to the
Truth Table as long as minimum set-up times are observed. Input data
is transferred to the outputs on the HIGH-to-LOW clock transitions.
MODE SELECT – TRUTH TABLE Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition
GUARANTEED OPERATING RANGES
