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74F543PC ,Octal Registered TransceiverFunctional Description Data I/O Control TableThe F543 contains two sets of eight D-type latches, wi ..
74F543SC ,Octal Registered TransceiverFunctional Description Data I/O Control TableThe F543 contains two sets of eight D-type latches, wi ..
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74F543SCX ,Octal Registered Transceiver74F543 Octal Registered TransceiverApril 1988Revised October 200074F543Octal Registered Transceiver
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74245-74LS245
3-STATE Octal Bus Transceiver
DM74LS245 3-STATE Octal Bus Transceiver August 1986 Revised March 2000 DM74LS245 3-STATE Octal Bus Transceiver General Description Features These octal bus transceivers are designed for asynchro- � Bi-Directional bus transceiver in a high-density 20-pin nous two-way communication between data buses. The package control function implementation minimizes external timing � 3-STATE outputs drive bus lines directly requirements. � PNP inputs reduce DC loading on bus lines The device allows data transmission from the A Bus to the � Hysteresis at bus inputs improve noise margins B Bus or from the B Bus to the A Bus depending upon the � Typical propagation delay times, port-to-port 8 ns logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the � Typical enable/disable times 17 ns buses are effectively isolated. � I (sink current) OL 24 mA � I (source current) OH −15 mA Ordering Code: Order Number Package Number Package Description DM74LS245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Enable Direction Operation G Control DIR L L B Data to A Bus L H A Data to B Bus HX Isolation H = HIGH Level L = LOW Level X = Irrelevant © 2000 DS006413
