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Partno Mfg Dc Qty AvailableDescript
SN74LS174NMOTN/a825avaiHEX D FLIP-FLOP
SN74LS174DMOTN/a28avaiHEX D FLIP-FLOP
SN54LS174JMOTN/a77avaiHEX D FLIP-FLOP
74LS174N/a700avaiHex/Quad D-Type Flip-Flops with Clear


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74LS174-SN54LS174J-SN74LS174D-SN74LS174N
Hex/Quad D-Type Flip-Flops with Clear
HEX D FLIP-FLOP
The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families. Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Asynchronous Common Reset Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)

VCC D5 D4 Q4 Q3D3 CP D0 D1 Q1 D2 Q2 GND
PIN NAMES LOADING (Note a)

D0–D5
Q0–Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
Q4 Q3 Q2 Q1 Q0D5 D4 D3 D2 D1 D0MR 10
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
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