74LCX74 ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant InputsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX74BQX ,Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant InputsElectrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-me ..
74LCX74M ,CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTFeaturesThe LCX74 is a dual D-type flip-flop with Asynchronous
74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
1/14September 2004 5V TOLERANT INPUTS HIGH SPEED:
fMAX = 150 MHz (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR and PR are independent of the clock and
accomplished by a low setting on the appropriate
input.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX74LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP
WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes Rev. 7
74LCX742/14
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table X : Don’t Care
74LCX743/14
Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays
Table 4: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
Table 5: Recommended Operating Conditions 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
74LCX744/14
Table 6: DC Specifications
Table 7: Dynamic Switching Characteristics 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX745/14
Table 8: AC Electrical Characteristics 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
Flip-Flop)
74LCX746/14
Figure 4: Test Circuit CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
74LCX747/14
Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Recovery Times (f=1MHz; 50% duty cycle)
