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74LCX16652MEAFAIRCHILN/a3avaiLow Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
74LCX16652MTDFAIRCHILN/a1070avaiLow Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
74LCX16652MTDXFAIRCHILDN/a630avaiLow Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
74LCX16652MTDXFSCN/a696avaiLow Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs


74LCX16652MTD ,Low Voltage Transceiver/Register with 5V Tolerant Inputs and OutputsFeaturesThe LCX16652 contains sixteen non-inverting bidirectional

74LCX16652MEA-74LCX16652MTD-74LCX16652MTDX
Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs February 1994 Revised April 2001 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description Features The LCX16652 contains sixteen non-inverting bidirectional5V tolerant inputs and outputs bus transceivers with 3-STATE outputs providing multi-2.3V–3.6V V specifications provided CC plexed transmission of data directly from the input bus or 5.7 ns t max (V = 3.3V), 20 μA I max PD CC CC from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goesPower down high impedance inputs and outputs to the HIGH logic level. Output Enable pins (OEAB, OEBA)Supports live insertion/withdrawal (Note 1) are provided to control the transceiver function (see Func- ±24 mA output drive (V = 3.0V) CC tional Description). Implements patented noise/EMI reduction circuitry The LCX16652 is designed for low-voltage (2.5V or 3.3V) Latch-up performance exceeds 500 mA V applications with capability of interfacing to a 5V signal CC environment.ESD performance: The LCX16652 is fabricated with an advanced CMOS tech- Human body model > 2000V nology to achieve high speed operation while maintaining Machine model > 200V CMOS low power dissipation. Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V and OE tied to GND through a resistor: the minimum CC value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LCX16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description A –A Data Register A Inputs/3-STATE Outputs 0 15 B –B Data Register B Inputs/3-STATE Outputs 0 15 CPAB , CPBA Clock Pulse Inputs n n SAB , SBA Select Inputs n n OEAB , OEBA Output Enable Inputs n n © 2001 DS012005
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