74LCX16373 ,Low-Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and OutputsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX16373G ,Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputsapplications with capability of interfacing to a 5V signalCCenvironment.
74LCX16373
Low-Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
1/10February 2003 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD= 5.4ns (MAX.)at VCC =3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL= 24mA (MIN)at VCC =3V PCI BUS LEVELS GUARANTEED AT24 mA BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR)= 2.0Vto 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH SERIES 16373 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM> 2000V (MIL STD 883 method 3015);> 200V
DESCRIPTIONThe 74LCX16373isa low voltage CMOS 16 BIT
D-TYPE LATCH with3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology.Itis ideal for low power and high
speed 3.3V applications;it canbe interfacedto 5V
signal environment for both inputs and outputs.
These 16bit D-TYPE latches are byte controlled two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE inputis heldata high level, the nQ
outputs will follow the data input precisely.
When the nLEis taken LOW, the nQ outputs will latched preciselyat the logic levelofD input
data.
While the (nOE) inputis low, the nQ outputs willbea normal logic state (highor low logic level) and
while high level the outputs willbeina high imped-
ance state. has same speed performanceat 3.3V than 5V
AC/ACT family, combined witha lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74LCX16373LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PIN CONNECTION
74LCX163732/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE: Don‘t Care: High Impedance:Q outputsare latchedat thetime whentheLE inputis takenlow
logic level.
IEC LOGIC SYMBOLS
74LCX163733/10
LOGIC DIAGRAMThis logic diagramhasnottobe usedto estimate propagation delays
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not impliedIO absolute maximum rating mustbe observedVO
RECOMMENDED OPERATING CONDITIONS Truth Table guaranteed: 1.5Vto 3.6VVIN from 0.8Vto2Vat VCC =3.0V
74LCX16373
4/10 SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS Numberof outputs definedas"n". Measured with "n-1" outputs switching from HIGHto LOWor LOWto HIGH. The remaining outputis
measuredinthe LOW state.
74LCX16373
5/10 ELECTRICAL CHARACTERISTICS Skewis defined astheabsolute value ofthedifference betweenthe actual propagation delayfor anytwo outputsofthe samedevice switch-
inginthe same direction, either HIGHor LOW (tOSLH =|tPLHm -tPLHn|, tOSHL =|tPHLm -tPHLn|) Parameter guaranteedby design
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCC xfIN +ICC/16 (per
circuit)
74LCX16373
6/10
TEST CIRCUIT=50pFor equivalent (includesjig and probe capacitance) =R1= 500Ω or equivalent =ZOUTof pulse generator (typically 50Ω)
WAVEFORM1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE
SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
