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74LCX02 ,Low Voltage Quad 2-Input NOR Gate with 5V Tolerant InputsMAXIMUM RATINGS*Symbol Parameter Value Condition UnitV DC Supply Voltage –0.5 to +7.0 VCCV DC Input ..
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75N75 , 75Amps, 75Volts N-CHANNEL POWER MOSTFET
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75T2089-IP , DTMF Transceivers
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75T2091-IH , DTMF Transceivers
74LCX00M-74LCX00MTR-74LCX00TTR
QUAD CMOS 2-INPUT NAND GATE WITH 5V TOLERANT INPUT
1/8September 2001 5V TOLERANT INPUTS HIGH SPEED :PD = 4.3ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00 LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTIONThe 74LCX00 is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LCX00LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
WITH 5V TOLERANT INPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
74LCX002/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
74LCX003/8
RECOMMENDED OPERATING CONDITIONS 1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
DC SPECIFICATIONS
DYNAMIC SWITCHING CHARACTERISTICS 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
74LCX004/8
AC ELECTRICAL CHARACTERISTICS 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
TEST CIRCUIT CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
74LCX005/8
WAVEFORM : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
