74HC595. Fast Delivery |IC PHOENIX CO.,LIMITED

74HC595. ,8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATELOGIC DIAGRAMTIMING CHART3/13M54/M74HC595PIN DESCRIPTION IEC LOGIC SYMBOLPIN No SYMBOL NAME AND FUN ..
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74HC595.
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE
M54 HC595
M74HC595 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
B1R
(Plastic Package)
ORDER CODES:
M54HC595F1R M74HC595M1R
M74HC595B1R M74HC595C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)= Internal HIGH SPEED
fMAX=55 MHz (TYP.) AT VCC =5V. LOWPOWER DISSIPATION
ICC =4 μA (MAX.) ATTA =25°C. HIGH NOISE IMMUNITY
VNIH =VNIL =28% VCC (MIN.). OUTPUT DRIVE CAPABILITY LSTTL LOADS FOR QA TO QH LSTTL LOADS FOR QH’. SYMMETRICAL OUTPUT IMPEDANCE
|IOH|= IOL=6 mA (MIN.) FOR QA TO QH
|IOH|= IOL=4 mA (MIN.) FOR QH’. BALANCEDPROPAGATION DELAYS
tPLH =tPHL. WIDE OPERATING VOLTAGE RANGE
VCC (OPR)=2V TO6V. PIN AND FUNCTION COMPATIBLE
WITH LSTTL 54/74LS595
DESCRIPTION
The M54/74HC595isa high speed CMOS 8-BIT
SHIFT REGISTERS/OUTPUT LATCHES (3-
STATE) fabricatedin siliconC2 MOS technology.It
has the same high speed performanceof LSTTL
combined with true CMOS low power consumption.
This device contains an 8-bit serial-in, parallel -out
shift register that feedsan 8-bit D-type storage reg-
ister. The storage register has8 3-STATE outputs.
Separate clocks are provided for both the shift reg-
ister and the storage register.
The shift register hasa direct-overriding clear, serial
input, and serial output (standard) pins for cascad-
ing. Both the shift register and storage register use
positive-edge triggered clocks.If both clocks are
connected together, the shift register state willal-
waysbe one clock pulse aheadof the storage reg-
ister.
All inputs are equipped with protection circuits
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS OUTPUTSI SCK SCLR RCK G X X X H QA THRU QH OUTPUTS DISABLE X X X L QA THRU QH OUTPUTS ENABLE X L X X SHIFT REGISTERIS CLEARED X X FIRST STAGE OF S.R. BECOMES”L” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY X X FIRST STAGE OF S.R. BECOMES ”H” OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY H X X STATE OF S.RIS NOT CHANGED X X X S.R. DATAIS STORED INTO STORAGE REGISTER X X X STORAGE REGISTER STATEIS NOT CHANGED DON’T CARE
LOGIC DIAGRAM
M54/M74HC595
LOGIC DIAGRAM
TIMING CHART
M54/M74HC595
IEC LOGIC SYMBOL
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Supply Voltage -0.5to+7 V DC Input Voltage -0.5to VCC+ 0.5 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA DC Output Current Per Output Pin QA-QH ±35 mA DC Output Current Per Output Pin QH’ ±25 mA
ICCor IGND DC VCCor Ground Current ±70 mA Power Dissipation 500(*) mW
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
Absolute MaximumRatings arethose values beyond whichdamage tothedevicemayoccur.Functional operation under theseconditionisnotimplied.
(*)500 mW:≅65oC derate to300mWby 10mW/oC:65o Cto85oC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply Voltage 2to6 V Input Voltage 0to VCC V Output Voltage 0to VCC V
Top Operating Temperature: M54HC Series
M74HC Series
-55to +125
-40to +85CC
tr,tf Input Rise and Fall Time VCC=2V 0to 1000 ns
VCC=4.5V 0to 500
VCC=6V 0to 400
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION2,3,4,5,7,15to QH Data Outputs QH’ Serial Data Outputs SCLR Shift Register Clear
Input SCK Shift Register Clock
Input G Output Enable Input SI Serial Data Input RCK Storage Register Clock
Input GND Ground (0V) VCC Positive Supply Voltage
M54/M74HC595
SPECIFICATIONSSymbol Parameter
Test Conditions Value
UnitVCC
(V) =25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage
2.0 1.5 1.5 1.54.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage
2.0 0.5 0.5 0.54.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level
Output Voltage
(for QH’ output)
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOH High Level
Output Voltage
(for QAto QH
outputs)
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-6.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage
(for QH’ output)
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.1
4.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 4.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.33 0.40
VOL Low Level Output
Voltage
(for QAto QH
outputs)
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.14.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 6.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 7.8 mA 0.18 0.26 0.33 0.40 Input Leakage
Current 6.0 VI =VCCor GND ±0.1 ±1 ±1 μA
IOZ 3 State Output
Off State Current 6.0 VI =VIHorVIL =VCCor GND
±0.5 ±5 ±10 μA
ICC Quiescent Supply
Current
6.0 VI =VCCor GND 4 40 80 μA
M54/M74HC595
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)Symbol Parameter
Test Conditions Value
UnitVCC
(V)
(pF) =25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
Output Transition
Time (Qn)
2.0 60 75 904.5 7 121518
6.0 6 101315
tTLH
tTHL
Output Transition
Time (QH’)
2.0 75 95 1154.5 8 151923
6.0 7 131620
tPLH
tPHL
Propagation
Delay Time
(SCK- QH’)
2.0 125 155 1904.5 15 25 31 38
6.0 13 21 26 32
tPLH
tPHL
Propagation
Delay Time
(SCLR- QH’)
2.0 175 220 2654.5 18 35 44 53
6.0 15 30 37 45
tPLH
tPHL
Propagation
Delay Time
(RCK- Qn)
2.0 150 190 2254.5 20 30 38 45
6.0 17 26 32 38
150 190 240 2854.5 25 38 48 57
6.0 22 32 41 48
tPZL
tPZH State Output
Enable Time
2.0 RL =1 KΩ 135 170 2054.5 15 27 34 41
6.0 13 23 29 35
150 RL =1 KΩ 175 220 2654.5 20 35 44 53
6.0 17 30 37 45
tPLZ
tPHZ State Output
Disable Time
2.0 RL =1 KΩ 150 190 2254.5 15 30 38 45
6.0 14 26 32 38
fMAX Maximum Clock
Frequency
6.0 17 4.8 44.5 30 50 24 20
6.0 35 59 28 24
5.2 14 4.2 3.44.5 26 40 21 17
6.0 31 45 25 20
tW(H) Minimum Pulse
Width
(SCK, RCK)
2.0 75 95 1104.5 6 151922
6.0 6 131619
tW(L) Minimum Pulse
Width
(SCLR)
2.0 75 95 1104.5 6 151922
6.0 6 131619 Minimum Set-up
Time
(SI- CCK)
2.0 50 65 754.5 5 101315
M54/M74HC595
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)Symbol Parameter
Test Conditions Value
UnitVCC
(V)
(pF) =25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max. Minimum Set-up
Time
(SCK- RCK)
2.0 75 95 1104.5 8 151922
6.0 6 131619 Minimum Set-up
Time
(SCRL- RCK)
2.0 100 125 1454.5 10 20 25 29
6.0 7 172125 Minimum Hold
Time
0004.5 0 0 0
6.0 0 0 0
tREM Minimum Clear
Remuval Time
2.0 50 65 754.5 3 101315
6.0 3 9 11 13
CIN Input Capacitance 5 10 10 10 pF
CPD(*) Power Dissipation
Capacitance
184 pF
(*) CPD isdefinedasthe valueofthe IC’sinternal equivalent capacitance which iscalculated fromthe operatingcurrent consumption without load.
(Referto Test Circuit).Average operting currentcanbe obtained bythefollowingequation. ICC(opr)=CPD •VCC •fIN+ICC
SWITCHING CHARACTERISTICS TEST WAVEFORM
WAVEFORM1 WAVEFORM2
M54/M74HC595

Partno	Mfg	Dc	Qty	Available	Descript
74HC595. \|74HC595	ST	N/a	3000	avai	8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE