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74HC4052BQ
Dual 4-channel analog multiplexer/demultiplexer
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common input/output (pin nZ). The common channel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pinE= LOW, one of the four switches is selected (low-impedance ON-state) with pins S0
and S1. When pinE= HIGH, all switches are in the high-impedance OFF-state,
independent of pins S0 and S1.
VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The VCC to GND ranges are 2.0 Vto 10.0 V for the 74HC4052 and 4.5Vto 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features and benefits Wide analog input voltage range from 5 V to +5V Low ON resistance:80 (typical) at VCC VEE =4.5V70 (typical) at VCC VEE =6.0V60 (typical) at VCC VEE =9.0V Logic level translation: to enable 5 V logic to communicate with 5 V analog signals Typical ‘break before make’ built-in Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Specified from 40 Cto +85 C and 40 Cto +125C
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 10 — 19 July 2012 Product data sheet
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating
4. Ordering informationTable 1. Ordering information
74HC4052
74HC4052N 40 C to +125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC4052D 40 C to +125C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74HC4052DB 40 C to +125C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74HC4052PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HC4052BQ 40 C to +125C DHVQFN16 plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5  0.85 mm
SOT763-1
74HCT4052
74HCT4052N 40 C to +125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4052D 40 C to +125C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT4052DB 40 C to +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT4052PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT4052BQ 40 C to +125C DHVQFN16 plastic dual-in line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5  0.85 mm
SOT763-1
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
5. Functional diagram
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
2Y0 1 independent input or output 2Y0
2Y2 2 independent input or output 2Y2 3 common input or output 2
2Y3 4 independent input or output 2Y3
2Y1 5 independent input or output 2Y1 6 enable input (active LOW)
VEE 7 negative supply voltage
GND 8 ground (0V) 9 select logic input 1 10 select logic input 0
1Y3 11 independent input or output 1Y3
1Y0 12 independent input or output 1Y0 13 common input or output 1
1Y1 14 independent input or output 1Y1
1Y2 15 independent input or output 1Y2
VCC 16 positive supply voltage
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
[1] H= HIGH voltage level;= LOW voltage level;= don’t care.
8. Limiting values
[1] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must
not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the
voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE.
[2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.
[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1]
LLLnY0 and nZ L H nY1 and nZ LnY2 and nZ HHnY3 and nZ X X none
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VEE= GND (ground=0 V).
VCC supply voltage [1] 0.5 +11.0 V
IIK input clamping current VI< 0.5 V or VI >VCC +0.5V - 20 mA
ISK switch clamping current VSW< 0.5 V or VSW >VCC +0.5V - 20 mA
ISW switch current 0.5V< VSW IEE supply current - 20 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [2]- 750 mW
SO16, (T)SSOP16, and DHVQFN16
package
[3]- 500 mW power dissipation per switch - 100 mW
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5. Recommended operating conditions
VCC supply voltage see Figure7
and Figure8
VCC GND 2.0 5.0 10.0 4.5 5.0 5.5 V
VCC VEE 2.0 5.0 10.0 2.0 5.0 10.0 V input voltage GND - VCC GND - VCC V
VSW switch voltage VEE -VCC VEE -VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall
rate
VCC= 2.0V - - 625 - - - ns/V
VCC= 4.5V - 1.67 139 - 1.67 139 ns/V
VCC =6.0V - - 83 - - - ns/V
VCC= 10.0V - - 31 - - - ns/V
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
10. Static characteristicsTable 6. RON resistance per switch for 74HC4052 and 74HCT4052
VI = VIH or VIL; for test circuit see Figure9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0V.
For 74HCT4052: VCC GND= 4.5 V and 5.5 V, VCC VEE= 2.0 V, 4.5 V, 6.0 V and 9.0V.
Tamb= 40 Cto+85C[1]
RON(peak) ON resistance (peak) Vis =VCCto VEE
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] --- 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A- 100 225 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A- 90 200 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A- 70 165 
RON(rail) ON resistance (rail) Vis =VEE
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] -150 - 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A- 80 175 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A- 70 150 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A- 60 130 
Vis =VCC
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] -150 - 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A- 90 200 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A- 80 175 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A- 65 150 
RON ON resistance mismatch
between channels
Vis =VCC to VEE
VCC = 2.0 V; VEE = 0 V [2] --- 
VCC = 4.5 V; VEE = 0 V - 9 - 
VCC = 6.0 V; VEE = 0 V - 8 - 
VCC = 4.5 V; VEE = 4.5 V - 6 - 
Tamb= 40Cto +125C
RON(peak) ON resistance (peak) Vis =VCCto VEE
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] --- 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A --270 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A --240 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --195 
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb =25C.
[2] When supply voltages (VCC VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of V, it is recommended to use these devices only for transmitting digital signals.
RON(rail) ON resistance (rail) Vis =VEE
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] --- 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A --210 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A --180 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --160 
Vis =VCC
VCC = 2.0 V; VEE = 0 V; ISW= 100 A [2] --- 
VCC = 4.5 V; VEE = 0 V; ISW= 1000 A --240 
VCC = 6.0 V; VEE = 0 V; ISW= 1000 A --210 
VCC = 4.5 V; VEE = 4.5 V; ISW = 1000 A --180 
Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 …continued
VI = VIH or VIL; for test circuit see Figure9.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
For 74HC4052: VCC GND or VCC VEE = 2.0 V, 4.5 V, 6.0 V and 9.0V.
For 74HCT4052: VCC GND= 4.5 V and 5.5 V, VCC VEE= 2.0 V, 4.5 V, 6.0 V and 9.0V.
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexerTable 7. Static characteristics for 74HC4052
Voltages are referenced to GND (ground=0V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Tamb= 40 Cto+85C[1]
VIH HIGH-level input
voltage
VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VCC = 9.0 V 6.3 4.7 - V
VIL LOW-level input
voltage
VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VCC = 9.0 V - 4.3 2.7 V input leakage current VEE = 0 V; VI =VCCor GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
IS(OFF) OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure11
per channel - - 1.0 A
all channels - - 2.0 A
IS(ON) ON-state leakage
current =VIHor VIL; VSW =VCC VEE;
VCC= 10.0 V; VEE = 0 V; see Figure12 2.0 A
ICC supply current VEE = 0 V; VI =VCCor GND; Vis =VEEor VCC;
Vos =VCCor VEE
VCC = 6.0 V - - 80.0 A
VCC = 10.0 V - - 160.0 A input capacitance - 3.5 - pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ - 12 - pF
Tamb= 40Cto +125C
VIH HIGH-level input
voltage
VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input
voltage
VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VCC = 9.0 V - - 2.7 V input leakage current VEE = 0 V; VI =VCCor GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb =25C.
IS(OFF) OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure11
per channel - - 1.0 A
all channels - - 2.0 A
IS(ON) ON-state leakage
current =VIHor VIL; VSW =VCC VEE;
VCC= 10.0 V; VEE = 0 V; see Figure12 2.0 A
ICC supply current VEE = 0 V; VI =VCCor GND; Vis =VEEor VCC;
Vos =VCCor VEE
VCC = 6.0 V - - 160.0 A
VCC = 10.0 V - - 320.0 A
Table 7. Static characteristics for 74HC4052 …continued
Voltages are referenced to GND (ground=0V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Table 8. Static characteristics for 74HCT4052
Voltages are referenced to GND (ground=0V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Tamb= 40 Cto+85C[1]
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 V input leakage current VI =VCCor GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A
IS(OFF) OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure11
per channel - - 1.0 A
all channels - - 2.0 A
IS(ON) ON-state leakage
current
VCC= 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure12 2.0 A
ICC supply current VI =VCCor GND; Vis =VEEor VCC;
Vos =VCCor VEE
VCC = 5.5 V; VEE = 0 V - - 80.0 A
VCC = 5.0 V; VEE = 5.0 V - - 160.0 A
ICC additional supply
current
per input; VI =VCC 2.1 V; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V 45 202.5 A input capacitance - 3.5 - pF
Csw switch capacitance independent pins nYn - 5 - pF
common pins nZ - 12 - pF
Tamb= 40Cto +125C
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 2.0 - - V
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb =25C.
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - - 0.8 V input leakage current VI =VCCor GND; VCC = 5.5 V; VEE = 0 V - - 1.0 A
IS(OFF) OFF-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure11
per channel - - 1.0 A
all channels - - 2.0 A
IS(ON) ON-state leakage
current
VCC = 10.0 V; VEE = 0 V; VI =VIHor VIL; VSW =VCC VEE; see Figure12 2.0 A
ICC supply current VI =VCCor GND; Vis =VEEor VCC;
Vos =VCCor VEE
VCC = 5.5 V; VEE = 0 V - - 160.0 A
VCC = 5.0 V; VEE = 5.0 V - - 320.0 A
ICC additional supply
current
per input; VI =VCC 2.1 V; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - 220.5 A
Table 8. Static characteristics for 74HCT4052 …continued
Voltages are referenced to GND (ground=0V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
11. Dynamic characteristicsTable 9. Dynamic characteristics for 74HC4052
GND=0 V; tr=tf =6ns; CL=50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Tamb= 40 Cto+85C[1]
tpd propagation delay Vis to Vos; RL=  ; see Figure13 [2]
VCC = 2.0 V; VEE= 0 V - 14 75 ns
VCC = 4.5 V; VEE =0 V - 5 15 ns
VCC = 6.0 V; VEE =0 V - 4 13 ns
VCC = 4.5 V; VEE= 4.5 V - 4 10 ns
ton turn-on time E, Sn to Vos; RL= ; see Figure14 [3]
VCC = 2.0 V; VEE= 0 V - 105 405 ns
VCC = 4.5 V; VEE= 0 V - 38 81 ns
VCC = 5.0 V; VEE =0 V; CL = 15 pF - 28 - ns
VCC = 6.0 V; VEE= 0 V - 30 69 ns
VCC = 4.5 V; VEE= 4.5 V - 26 58 ns
toff turn-off time E, Sn to Vos; RL =1 k; see Figure14 [4]
VCC = 2.0 V; VEE= 0 V - 74 315 ns
VCC = 4.5 V; VEE= 0 V - 27 63 ns
VCC = 5.0 V; VEE =0 V; CL = 15 pF - 21 - ns
VCC = 6.0 V; VEE= 0 V - 22 54 ns
VCC = 4.5 V; VEE= 4.5 V - 22 48 ns
CPD power dissipation
capacitance
per switch; VI = GND to VCC [5] -57 - pF
Tamb= 40Cto +125C
tpd propagation delay Vis to Vos; RL=  ; see Figure13 [2]
VCC = 2.0 V; VEE =0 V - - 90 ns
VCC = 4.5 V; VEE =0 V - - 18 ns
VCC = 6.0 V; VEE =0 V - - 15 ns
VCC = 4.5 V; VEE= 4.5 V - - 12 ns
ton turn-on time E, Sn to Vos; RL= ; see Figure14 [3]
VCC = 2.0 V; VEE =0 V - - 490 ns
VCC = 4.5 V; VEE =0 V - - 98 ns
VCC = 6.0 V; VEE =0 V - - 83 ns
VCC = 4.5 V; VEE= 4.5 V - - 69 ns
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPZH and tPZL.
[4] toff is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2fi N + {(CL +Csw)  VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
{(CL +Csw)  VCC2  fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
toff turn-off time E, Sn to Vos; RL =1 k; see Figure14 [4]
VCC = 2.0 V; VEE =0 V - - 375 ns
VCC = 4.5 V; VEE =0 V - - 75 ns
VCC = 6.0 V; VEE =0 V - - 64 ns
VCC = 4.5 V; VEE= 4.5 V - - 57 ns
Table 9. Dynamic characteristics for 74HC4052 …continued
GND=0 V; tr=tf =6ns; CL=50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Table 10. Dynamic characteristics for 74HCT4052
GND=0 V; tr=tf =6ns; CL=50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.
Tamb= 40 Cto+85C[1]
tpd propagation delay Vis to Vos; RL= ; see Figure13 [2]
VCC = 4.5 V; VEE =0 V - 5 15 ns
VCC = 4.5 V; VEE= 4.5 V - 4 10 ns
ton turn-on time E, Sn to Vos; RL =1 k; see Figure14 [3]
VCC = 4.5 V; VEE= 0 V - 41 88 ns
VCC = 5.0 V; VEE =0 V; CL = 15 pF - 18 - ns
VCC = 4.5 V; VEE= 4.5 V - 28 60 ns
toff turn-off time E, Sn to Vos; RL =1 k; see Figure14 [4]
VCC = 4.5 V; VEE= 0 V - 26 63 ns
VCC = 5.0 V; VEE =0 V; CL = 15 pF - 13 - ns
VCC = 4.5 V; VEE= 4.5 V - 21 48 ns
CPD power dissipation
capacitance
per switch; VI = GND to VCC 1.5V [5] -57 - pF
NXP Semiconductors 74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPHL and tPLH.
[3] ton is the same as tPZH and tPZL.
[4] toff is the same as tPHZ and tPLZ.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2fi N + {(CL +Csw)  VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
N = number of inputs switching;
{(CL +Csw)  VCC2  fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
Tamb= 40Cto +125C
tpd propagation delay Vis to Vos; RL= ; see Figure13 [2]
VCC = 4.5 V; VEE= 0 V --18 ns
VCC = 4.5 V; VEE= 4.5 V - - 12 ns
ton turn-on time E, Sn to Vos; RL =1 k; see Figure14 [3]
VCC = 4.5 V; VEE= 0 V --105 ns
VCC = 4.5 V; VEE= 4.5 V - - 72 ns
toff turn-off time E, Sn to Vos; RL =1 k; see Figure14 [4]
VCC = 4.5 V; VEE= 0 V --75 ns
VCC = 4.5 V; VEE= 4.5 V - - 57 ns
Table 10. Dynamic characteristics for 74HCT4052 …continued
GND=0 V; tr=tf =6ns; CL=50 pF; for test circuit see Figure 15.
Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output.

Partno	Mfg	Dc	Qty	Available	Descript
74HC4052BQ	NXP	N/a	50	avai	Dual 4-channel analog multiplexer, demultiplexer