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74HC4049DNXPN/a6avaiHex inverting HIGH-to-LOW level shifter
74HC4049NMOTN/a1500avai74HC4049; Hex inverting high-to-low level shifter


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74HC4049D-74HC4049N
Hex inverting HIGH-to-LOW level shifter
1. General description
The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage
tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting
applications.
2. Features and benefits
Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125C
3. Ordering information

74HC4049
Hex inverting HIGH-to-LOW level shifter
Rev. 6 — 8 January 2013 Product data sheet
Table 1. Ordering information

74HC4049N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC4049D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HC4049DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC4049PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter
4. Functional diagram

5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter
5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60C.
Table 2. Pin description

VCC 1 supply voltage
1Y to 6Y 2, 4, 6, 10, 12, 15 output
1A to 6A 3, 5, 7, 9, 11, 14 input
GND 8 ground (0V)
n.c. 13, 16 not connected
Table 3. Function table[1]

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
VIK input clamping voltage 0.5 +16 V
IIK input clamping current VI < 0.5V 20 - mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16, SSOP16 and TSSOP16 packages [2]- 500 mW
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 V input voltage 0 - 15 V output voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V; VI= 2.0 V - - 625 ns/V
VCC = 4.5 V; VI= 4.5 V - 1.67 139 ns/V
VCC = 6.0 V; VI= 6.0 V- - 83 ns/V
VCC = 6.0 V; VI= 10.0 V- - 81 ns/V
VCC = 6.0 V; VI= 15.0 V- - 83 ns/V
Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground=0V).
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.3 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.1 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.7 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 1.8 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.3 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4.0 mA; VCC= 4.5V 3.98 - - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 - - 5.34 - 5.2 - V
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter
10. Dynamic characteristics

VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - - 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - - 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - - 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 4.5V - - 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - - 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A= 15 V; VCC= 2.0 V to
6.0V 0.5 - 5.0 - 5.0 A
ICC supply current VI= 15 Vor GND; IO =0A;
VCC =6.0V 2.0 - 20 - 40 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics

Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure8.
tpd propagation
delay
nA to nY; see Figure7 [1]
VCC = 2.0 V - 28 85 - 105 - 130 ns
VCC = 4.5 V - 10 17 - 21 - 26 ns
VCC =5V; CL =15pF - 8 - - - - - ns
VCC = 6.0 V - 8 14 - 18 - 22 ns transition
time
Yn; see Figure7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter

[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
11. Waveforms

CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[3] -14 - - - - - pF
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure8.
Table 8. Measurement points

74HC4049 0.5VCC 0.5VCC
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter

Table 9. Test data

74HC4049 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
NXP Semiconductors 74HC4049
Hex inverting HIGH-to-LOW level shifter
12. Package outline

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