74HC3G14DC-74HC3G14DP-74HCT3G14DP Fast Delivery |IC PHOENIX CO.,LIMITED

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74HC3G14DC-74HC3G14DP-74HCT3G14DP
Triple inverting Schmitt trigger
1. General description
The 74HC3G14; 74HCT3G14 is a triple inverter with Schmitt-trigger inputs. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals
into sharply defined jitter-free output signals.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Complies with JEDEC standard no. 7A Input levels: For 74HC3G14: CMOS level For 74HCT3G14: TTL level High noise immunity Low power dissipation Balanced propagation delays Unlimited input rise and fall times Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and 40 Cto+125C
3. Applications Wave and pulse shaper for highly noisy environments Astable multivibrators Monostable multivibrators
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
Rev. 5 — 9 December 2013 Product data sheet
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
4. Ordering information
5. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
Table 1. Ordering information
74HC3G14DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74HCT3G14DP
74HC3G14DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74HCT3G14DC
74HC3G14GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; terminals; body 3  2  0.5 mm
SOT996-2
74HCT3G14GD
Table 2. Marking
74HC3G14DP H14
74HCT3G14DP T14
74HC3G14DC H14
74HCT3G14DC T14
74HC3G14GD H14
74HCT3G14GD T14
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
7. Pinning information
7.1 Pinning
7.2 Pin description
8. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
Table 3. Pin description
1A, 2A, 3A 1, 3, 6 data input
GND 4 ground (0 V) , 2Y, 3Y 7, 5, 2 data output
VCC 8 supply voltage
Table 4. Function table[1]
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
9. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI >VCC+ 0.5 V [1]- 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V [1]- 20 mA output current VO = 0.5 V to VCC +0.5V [1]- 25 mA
ICC supply current [1] -+50 mA
IGND ground current [1] 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2] -300 mW
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
11. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25 C.
74HC3G14
VOH HIGH-level
output voltage = VT+ or VT = 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V = 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V = 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V = 4.0 mA; VCC= 4.5V 4.18 4.32 - 4.13 - 3.7 - V = 5.2 mA; VCC= 6.0V 5.68 5.81 - 5.63 - 5.2 - V
VOL LOW-level
output voltage = VT+ or VT = 20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V = 20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V = 20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V = 5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply current per input pin; VCC =6.0V; =VCCor GND; IO =0A; - 1.0 - 10 - 20 A input
capacitance
-2.0 - - - - - pF
74HCT3G14
VOH HIGH-level
output voltage = VT+ or VT = 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V = 4.0 mA; VCC= 4.5V 4.18 4.32 - 4.13 - 3.7 - V
VOL LOW-level
output voltage = VIH or VIL = 20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V = 4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =5.5V - - 0.1 - 1.0 - 1.0 A
ICC supply current per input pin; VCC =5.5V; =VCCor GND; IO =0A; - 1.0 - 10 - 20 A
ICC additional
supply current
per input;
VCC= 4.5Vto 5.5V; =VCC 2.1 V; IO =0A - 300 - 375 - 410 A input
capacitance
-2.0 - - - - - pF
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
Table 8. Transfer characteristics
Voltages are referenced to GND (ground=0 V); for test circuit see Figure11.
74HC3G14
VT+ positive-going
threshold voltage
see Figure 6, Figure7
VCC = 2.0 V 1.00 1.18 1.50 1.00 1.50 1.50 V
VCC = 4.5 V 2.30 2.60 3.15 2.30 3.15 3.15 V
VCC = 6.0 V 3.00 3.46 4.20 3.00 4.20 4.20 V
VT negative-going
threshold voltage
see Figure 6, Figure7
VCC = 2.0 V 0.30 0.60 0.90 0.30 0.90 0.90 V
VCC = 4.5 V 1.13 1.47 2.00 1.13 2.00 2.00 V
VCC = 6.0 V 1.50 2.06 2.60 1.50 2.60 2.60 V hysteresis voltage (VT+ VT); see Figure6,
Figure 7 and Figure9
VCC = 2.0 V 0.30 0.60 1.00 0.30 1.00 1.00 V
VCC = 4.5 V 0.60 1.13 1.40 0.60 1.40 1.40 V
VCC = 6.0 V 0.80 1.40 1.70 0.80 1.70 1.70 V
74HCT3G14
VT+ positive-going
threshold voltage
see Figure 6, Figure7
VCC = 4.5 V 1.20 1.58 1.90 1.20 1.90 1.90 V
VCC = 5.5 V 1.40 1.78 2.10 1.40 2.10 2.10 V
VT negative-going
threshold voltage
see Figure 6, Figure7
VCC = 4.5 V 0.50 0.87 1.20 0.50 1.20 1.20 V
VCC = 5.5 V 0.60 1.11 1.40 0.60 1.40 1.40 V hysteresis voltage (VT+ VT); see Figure6,
Figure 7 and Figure8
VCC = 4.5 V 0.40 0.71 - 0.40 - - V
VCC = 5.5 V 0.40 0.67 - 0.40 - - V
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
11.1 Waveforms transfer characteristics
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
12. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL
[2] tt is the same as tTLH and tTHL
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for test circuit see Figure11.
74HC3G14
tpd propagation delay nAto nY; see Figure10 [1]
VCC = 2.0 V - 53 125 - 155 190 ns
VCC = 4.5 V - 16 25 - 31 38 ns
VCC = 6.0V - 13 21 - 26 32 ns transition time nY; see Figure10 [2]
VCC = 2.0V - 20 75 - 95 110 ns
VCC = 4.5V - 7 15 - 19 22 ns
VCC = 6.0V - 5 13 - 16 19 ns
CPD power dissipation
capacitance = GND to VCC [3] -10 - - - - pF
74HCT3G14
tpd propagation delay nAto nY; see Figure10 [1]
VCC = 4.5V - 21 32 - 40 48 ns transition time nY; see Figure10 [2]
VCC = 4.5V - 6 15 - 19 22 ns
CPD power dissipation
capacitance = GND to VCC  1.5 V [3] -10 - - - - pF
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
13. Waveforms
Table 10. Measurement points
74HC3G14 0.5VCC 0.5VCC
74HCT3G14 1.3V 1.3V
NXP Semiconductors 74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
Table 11. Test data
74HC3G14 GND to VCC  6ns 50 pF 1k open
74HCT3G14 GND to 3.0 V  6ns 50 pF 1k open

Partno	Mfg	Dc	Qty	Available	Descript
74HC3G14DC	NXP/PHIL	N/a	9000	avai	74HC3G14; 74HCT3G14; Inverting Schmitt-triggers
74HC3G14DP	NXP	N/a	31200	avai	Triple inverting Schmitt trigger
74HCT3G14DP	NXP/PHIL	N/a	12000	avai	Triple inverting Schmitt trigger