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74HC32D from SGS, 340pcs , SOP,Quad 2-input OR gate
Partno Mfg Dc Qty Available
74HC32D SGS N/a 340
74HC32D from MOT, Motorola 632pcs,Quad 2-input OR gate
74HC32D from PHI, Philips 5000pcs,Quad 2-input OR gate
74HC32D from PH, 2350pcs , SOP14,Quad 2-input OR gate
74HC32D from PHILIPS, Philips 5000pcs , SOP,Quad 2-input OR gate
74HC32D from PHILIPS  , Philips 79758pcs,Quad 2-input OR gate
74HC32D from NXP , NXP Semiconductors 62500pcs,Quad 2-input OR gate
74HC32D from TI  , Texas Instruments 294pcs,Quad 2-input OR gate
74HC32D from NXPLIPS, NXP Semiconductors 13368pcs,Quad 2-input OR gate
74HC32D from FAIRCHIL, Fairchild Semiconductor 76pcs , SSOP14,Quad 2-input OR gate
74HC32D from HYNIX, 690pcs , SOP,Quad 2-input OR gate
74HC32D 1596pcs , SOP,Quad 2-input OR gate
74HC32D from TI, Texas Instruments 2465pcs , SOP-14,Quad 2-input OR gate
74HC32D from PHILIPS Pb-free, Philips 4661pcs , SOP,Quad 2-input OR gate

INTEGRATED CIRCUITSDATA SHEET74HC32; 74HCT32Quad 2-input OR gateProduct specification 2003 Dec 12Supersedes data of 2003 Aug 29Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32General descriptionThe 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC2. INTEGRATED CIRCUITSDATA SHEET74HC32; 74HCT32Quad 2-input OR gateProduct specification 2003 Dec 12Supersedes data of 2003 Aug 29Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Complies with JEDEC standard JESD7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Input levels: For 74HC32: CMOS level For 74HCT32: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40C to +85C and from 40C to +125C74HC32; 74HCT32NXP SemiconductorsQuad 2-input OR gate3. Ordering information Table 1. Ordering informationType number PackageTemperature range Name Description Version74HC32N40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-174HCT32N74HC32D40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-13.9 mm74HCT32D74HC32DB40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body SOT337-1width 5.3 mm74HCT32DB74HC32PW40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1body width 4.4 mm74HCT32PW74HC32BQ40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1thin quad flat package; no leads; 14 terminals; 74HCT32BQbody 2.5 3 0.85 mm4. Functional diagram 1≥1324≥1611A31Y 521B42A62Y952B≥181093A83Y103BA12 124A≥1114Y11Y134B13Bmna242 mna243 mna241Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. GENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si-gate CMOS deviceand is pin compatible with low power Schottky TTL• Symmetrical output impedance(LSTTL). They are specified in compliance with JEDEC• High noise immunitystandard no. 7A.• Low power dissipationThe 74HC/HCT32 provides the 2-input OR function.• Balanced propagation delays• ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 ns.amb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt /t propagation delay nA, nB to nY C = 15 pF; V=5V69nsPHL PLH L CCC input capacitance 3.5 3.5 pFIC power dissipation capacitance per gate notes 1 and 2 16 28 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW).PD D2 2P =C × V × f × N+ Σ(C × V × f ) where:D PD CC i L CC of = input frequency in MHz;if = output frequency in MHz;oC = output load capacitance in pF;LV = supply voltage in Volts;CCN = total load switching outputs;2Σ(C × V × f ) = sum of the outputs.L CC o2. For 74HC32 the condition is V = GND to V .I CCFor 74HCT32 the condition is V = GND to V - 1.5 V.I CCFUNCTION TABLESee note 1.INPUT OUTPUTnA nB nYLLLLH HHLHHHHNote1. H = HIGH voltage level;L = LOW voltage level.2003 Dec 12 2Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32ORDERING INFORMATIONPACKAGETYPE NUMBERTEMPERATUREPINS PACKAGE MATERIAL CODERANGE74HC32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HCT32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HC32D - 40 to +125 °C 14 SO14 plastic SOT108-174HCT32D - 40 to +125 °C 14 SO14 plastic SOT108-174HC32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HCT32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HC32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HCT32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HC32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-174HCT32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-1PINNINGPIN SYMBOL DESCRIPTION1 1A data inputhandbook, halfpage1A 1 14 VCC2 1B data input1B 2 134B3 1Y data output1Y 3 124A4 2A data input5 2B data input 2A 4 1132 4Y6 2Y data output2B 5 10 3B7 GND ground (0 V)2Y 6 9 3A8 3Y data outputGND 7 8 3Y9 3A data inputMNA24010 3B data input11 4Y data output12 4A data inputFig.1 GENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si-gate CMOS deviceand is pin compatible with low power Schottky TTL• Symmetrical output impedance(LSTTL). They are specified in compliance with JEDEC• High noise immunitystandard no. 7A.• Low power dissipationThe 74HC/HCT32 provides the 2-input OR function.• Balanced propagation delays• ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 ns.amb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt /t propagation delay nA, nB to nY C = 15 pF; V=5V69nsPHL PLH L CCC input capacitance 3.5 3.5 pFIC power dissipation capacitance per gate notes 1 and 2 16 28 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW).PD D2 2P =C × V × f × N+ Σ(C × V × f ) where:D PD CC i L CC of = input frequency in MHz;if = output frequency in MHz;oC = output load capacitance in pF;LV = supply voltage in Volts;CCN = total load switching outputs;2Σ(C × V × f ) = sum of the outputs.L CC o2. For 74HC32 the condition is V = GND to V .I CCFor 74HCT32 the condition is V = GND to V - 1.5 V.I CCFUNCTION TABLESee note 1.INPUT OUTPUTnA nB nYLLLLH HHLHHHHNote1. H = HIGH voltage level;L = LOW voltage level.2003 Dec 12 2Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32ORDERING INFORMATIONPACKAGETYPE NUMBERTEMPERATUREPINS PACKAGE MATERIAL CODERANGE74HC32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HCT32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HC32D - 40 to +125 °C 14 SO14 plastic SOT108-174HCT32D - 40 to +125 °C 14 SO14 plastic SOT108-174HC32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HCT32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HC32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HCT32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HC32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-174HCT32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-1PINNINGPIN SYMBOL DESCRIPTION1 1A data inputhandbook, halfpage1A 1 14 VCC2 1B data input1B 2 134B3 1Y data output1Y 3 124A4 2A data input5 2B data input 2A 4 1132 4Y6 2Y data output2B 5 10 3B7 GND ground (0 V)2Y 6 9 3A8 3Y data outputGND 7 8 3Y9 3A data inputMNA24010 3B data input11 4Y data output12 4A data inputFig.1 Pin configuration DHVQFN145.2 Pin description Table 2. Pin descriptionSymbol Pin Description1A to 4A 1, 4, 9, 12 data input1B to 4B 2, 5, 10,13 data input1Y to 4Y 3, 6, 8, 11 data outputGND 7 ground (0 V)V 14 supply voltageCC6. GENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si-gate CMOS deviceand is pin compatible with low power Schottky TTL• Symmetrical output impedance(LSTTL). They are specified in compliance with JEDEC• High noise immunitystandard no. 7A.• Low power dissipationThe 74HC/HCT32 provides the 2-input OR function.• Balanced propagation delays• ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 ns.amb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt /t propagation delay nA, nB to nY C = 15 pF; V=5V69nsPHL PLH L CCC input capacitance 3.5 3.5 pFIC power dissipation capacitance per gate notes 1 and 2 16 28 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW).PD D2 2P =C × V × f × N+ Σ(C × V × f ) where:D PD CC i L CC of = input frequency in MHz;if = output frequency in MHz;oC = output load capacitance in pF;LV = supply voltage in Volts;CCN = total load switching outputs;2Σ(C × V × f ) = sum of the outputs.L CC o2. For 74HC32 the condition is V = GND to V .I CCFor 74HCT32 the condition is V = GND to V - 1.5 V.I CCFUNCTION TABLESee note 1.INPUT OUTPUTnA nB nYLLLLH HHLHHHHNote1. H = HIGH voltage level;L = LOW voltage level.2003 Dec 12 2Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32ORDERING INFORMATIONPACKAGETYPE NUMBERTEMPERATUREPINS PACKAGE MATERIAL CODERANGE74HC32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HCT32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HC32D - 40 to +125 °C 14 SO14 plastic SOT108-174HCT32D - 40 to +125 °C 14 SO14 plastic SOT108-174HC32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HCT32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HC32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HCT32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HC32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-174HCT32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-1PINNINGPIN SYMBOL DESCRIPTION1 1A data inputhandbook, halfpage1A 1 14 VCC2 1B data input1B 2 134B3 1Y data output1Y 3 124A4 2A data input5 2B data input 2A 4 1132 4Y6 2Y data output2B 5 10 3B7 GND ground (0 V)2Y 6 9 3A8 3Y data outputGND 7 8 3Y9 3A data inputMNA24010 3B data input11 4Y data output12 4A data inputFig.1 Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Complies with JEDEC standard JESD7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Input levels: For 74HC32: CMOS level For 74HCT32: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40C to +85C and from 40C to +125C74HC32; 74HCT32NXP SemiconductorsQuad 2-input OR gate3. Ordering information Table 1. Ordering informationType number PackageTemperature range Name Description Version74HC32N40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-174HCT32N74HC32D40 C to +125 C SO14 plastic small outline package; 14 leads; body width SOT108-13.9 mm74HCT32D74HC32DB40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body SOT337-1width 5.3 mm74HCT32DB74HC32PW40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1body width 4.4 mm74HCT32PW74HC32BQ40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1thin quad flat package; no leads; 14 terminals; 74HCT32BQbody 2.5 3 0.85 mm4. Functional diagram 1≥1324≥1611A31Y 521B42A62Y952B≥181093A83Y103BA12 124A≥1114Y11Y134B13Bmna242 mna243 mna241Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. GENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si-gate CMOS deviceand is pin compatible with low power Schottky TTL• Symmetrical output impedance(LSTTL). They are specified in compliance with JEDEC• High noise immunitystandard no. 7A.• Low power dissipationThe 74HC/HCT32 provides the 2-input OR function.• Balanced propagation delays• ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 ns.amb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt /t propagation delay nA, nB to nY C = 15 pF; V=5V69nsPHL PLH L CCC input capacitance 3.5 3.5 pFIC power dissipation capacitance per gate notes 1 and 2 16 28 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW).PD D2 2P =C × V × f × N+ Σ(C × V × f ) where:D PD CC i L CC of = input frequency in MHz;if = output frequency in MHz;oC = output load capacitance in pF;LV = supply voltage in Volts;CCN = total load switching outputs;2Σ(C × V × f ) = sum of the outputs.L CC o2. For 74HC32 the condition is V = GND to V .I CCFor 74HCT32 the condition is V = GND to V - 1.5 V.I CCFUNCTION TABLESee note 1.INPUT OUTPUTnA nB nYLLLLH HHLHHHHNote1. H = HIGH voltage level;L = LOW voltage level.2003 Dec 12 2Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32ORDERING INFORMATIONPACKAGETYPE NUMBERTEMPERATUREPINS PACKAGE MATERIAL CODERANGE74HC32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HCT32N - 40 to +125 °C 14 DIP14 plastic SOT27-174HC32D - 40 to +125 °C 14 SO14 plastic SOT108-174HCT32D - 40 to +125 °C 14 SO14 plastic SOT108-174HC32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HCT32DB - 40 to +125 °C 14 SSOP14 plastic SOT337-174HC32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HCT32PW - 40 to +125 °C 14 TSSOP14 plastic SOT402-174HC32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-174HCT32BQ - 40 to +125 °C 14 DHVQFN14 plastic SOT762-1PINNINGPIN SYMBOL DESCRIPTION1 1A data inputhandbook, halfpage1A 1 14 VCC2 1B data input1B 2 134B3 1Y data output1Y 3 124A4 2A data input5 2B data input 2A 4 1132 4Y6 2Y data output2B 5 10 3B7 GND ground (0 V)2Y 6 9 3A8 3Y data outputGND 7 8 3Y9 3A data inputMNA24010 3B data input11 4Y data output12 4A data inputFig.1 INTEGRATED CIRCUITSDATA SHEET74HC32; 74HCT32Quad 2-input OR gateProduct specification 2003 Dec 12Supersedes data of 2003 Aug 29Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32Logic diagram (one gate)74HC_HCT32 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.Product data sheet Rev. 5 — 4 September 2012 2 of 1774HC32; 74HCT32NXP SemiconductorsQuad 2-input OR gate5. Pinning information5.1 Pinning terminal 11A 1 14 VCCindex area2 131B 4B1B 2 13 4B1Y 3 12 4A1Y 3 12 4A2A 4 32 11 4Y2A 4 32 11 4Y2B 5 (1) 10 3BGND2B 5 10 3B6 92Y 3A2Y 6 9 3A7 8 001aad102GND 3Y001aad101 Transparent top view(1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input.Fig 4. General descriptionThe 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC2. INTEGRATED CIRCUITSDATA SHEET74HC32; 74HCT32Quad 2-input OR gateProduct specification 2003 Dec 12Supersedes data of 2003 Aug 29Philips Semiconductors Product specificationQuad 2-input OR gate 74HC32; 74HCT32

74HC32D ,Quad 2-input OR gatePin configuration DHVQFN145.2 Pin description Table 2. Pin descriptionSymbol Pin Description1A to 4 ..
74HC32DB ,Quad 2-input OR gateGENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si- ..
74HC32DB ,Quad 2-input OR gateGENERAL DESCRIPTION• Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT32 is a high-speed Si- ..
74HC32N ,74HC32; 74HCT32; Quad 2-input OR gateINTEGRATED CIRCUITSDATA SHEET74HC32; 74HCT32Quad 2-input OR gateProduct specification 2003 Dec 12Sup ..
74HC32PW ,74HC32; 74HCT32; Quad 2-input OR gatePin configuration DIP14, SO14 and (T)SSOP14 Fig 5.
74LVC821AD ,10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC821ADB ,10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821APW ,10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
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