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74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74LVC74A ,positive-edge trigger
74HC2G86DC
Dual 2-input EXCLUSIVE-OR gate
1. General descriptionThe 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include
clamp diodes that enable the use of current limiting resistors to interface inputs to voltages
in excess of VCC.
2. Features and benefits Wide supply voltage range from 2.0 Vto 6.0V Input levels: For 74HC2G86: CMOS level For 74HCT2G86: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
Rev. 4 — 14 March 2014 Product data sheet
Table 1. Ordering information
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
4. Marking[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 2. Marking code
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description[1] H = HIGH voltage level; L = LOW voltage level.
Table 3. Pin description
Table 4. Function table[1]
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
8. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
10. Static characteristics
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Table 6. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V).
Table 7. Static characteristicsVoltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
Table 7. Static characteristics …continuedVoltages are referenced to GND (ground = 0 V).
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
11. Dynamic characteristics[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTLH and tTHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
Table 8. Dynamic characteristicsVoltages are referenced to GND (ground =0 V); for test circuit, see Figure7.
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
12. Waveforms
Table 9. Measurement points
NXP Semiconductors 74HC2G86; 74HCT2G86
Dual 2-input EXCLUSIVE-OR gate
Table 10. Test data
