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74HC299D from PHI  , Philips 82pcs,74HC/HCT299; 8-bit universal shift register; 3-state
Partno Mfg Dc Qty Available
74HC299D PHI   N/a 82
74HC299D from PHILIPS, Philips 24pcs , SO-20,74HC/HCT299; 8-bit universal shift register; 3-state
74HC299D from NXP, NXP Semiconductors 2pcs , SOP20L,74HC/HCT299; 8-bit universal shift register; 3-state

INTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines74HC/HCT2998-bit universal shift register; 3-stateDecember 1990Product specificationFile under Integrated Circuits, IC06Philips Semiconductors Product specification8-bit universal shift register; 3-state 74HC/HCT299GENERAL DESCRIPTION 2 nset to the high-impedance OFF-state. In this condition, theThe 74HC/HCT299 are high-speed Si-gate CMOS devicesshift, hold, load and reset operations can still occur. Theand are pin compatible with low power Schottky TTL3-state buffers are also disabled by HIGH signals on both(LSTTL). They are specified in compliance with JEDECS and S , when in preparation for a parallel load0 1standard no. 7A.operation.QUICK REFERENCE DATAGND = 0 V; T =25 °C; t =t = 6 nsamb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCT t propagation delay C = 15 pF; V =5 VtPHL/ PLH L CCCP to Q , Q 20 19 ns0 7CP to I/O 20 19 nsnt MR to Q , Q or I/O 20 23 nsPHL 0 7 nf maximum clock frequency 50 46 MHzmaxC input capacitance 3.5 3.5 pFIC input/output capacitance 10 10 pFI/OC power dissipation capacitance per package notes 1 and 2 120 125 pFPDNotes1. C is used to determine the dynamic power2. For HC the condition is V = GND to VPDI CCdissipation (P in μW):D For HCT the condition is V = GND to V - 1.5 VI CC2 2P =C × V × f + ∑ (C × V × f ) where:D PD CC i L CC of = input frequency in MHzORDERING INFORMATIONif = output frequency in MHzoSee “74HC/HCT/HCU/HCMOS Logic Package2∑ (C × V × f ) = sum of outputs Information”.L CC oC = output load capacitance in pFLV = supply voltage in VCCDecember 1990 2Philips Semiconductors Product specification8-bit universal shift register; 3-state 74HC/HCT299PIN DESCRIPTIONPIN NO. SYMBOL NAME AND FUNCTION1, 19 S , S mode select inputs0 12, 3 OE , OE 3-state output enable inputs (active LOW)1 27, 13, 6, 14, 5, 15, 4, 16 I/O to I/O parallel data inputs or 3-state parallel outputs (bus driver)0 78, 17 Q , Q serial outputs (standard output)0 79 MR asynchronous master reset input (active LOW)10 GND ground (0 V)11 D serial data shift-right inputSR12 CP clock input (LOW-to-HIGH, edge-triggered)18 D serial data shift-left inputSL20 V positive supply voltageCCFig.1 General descriptionThe 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which arepin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified incompliance with JEDEC standard no. 7A.The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and theinterstage logic necessary to perform synchronous shift-right, shift-left, parallel load andhold operations. An operation is determined by the mode select inputs S0 and S1, asshown in Table 3.Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as datainputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion inserial shifting of longer words.A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CPinputs and resets the flip-flops. All other state changes are initiated by the rising edge ofthe clock pulse. Inputs can change when the clock is in either state, provided that therecommended set-up and hold times are observed.A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-statebuffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,the shift, hold, load and reset operations still occur when preparing for a parallel loadoperation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.2.

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