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74HC280N from NSC, National Semiconductor 400pcs , DIP,74HC/HCT280; 9-bit odd/even parity generator/checker
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74HC280N NSC N/a 400
74HC280N from PHIL, Philips 18400pcs , DIP-14,74HC/HCT280; 9-bit odd/even parity generator/checker
74HC280N from PHI, Philips 18975pcs , DIP-24,74HC/HCT280; 9-bit odd/even parity generator/checker

APPLICATIONS(LSTTL). They are specified in compliance with JEDECstandard no. 7A.• 25-line parity generator/checkerThe 74HC/HCT280 are 9-bit parity generators or checkers• 81-line parity generator/checkercommonly used to detect errors in high-speed dataQUICK REFERENCE DATAGND = 0 V; T =25°C; t =t = 6 nsamb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt / t propagation delay C = 15 pF; V =5 VPHL PLH L CCI to ∑ 17 18 nsn EI to ∑ 20 22 nsn OC input capacitance 3.5 3.5 pFIC power dissipationcapacitance per package notes 1 and 2 65 65 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW):PD D2 2P =C × V × f +∑ (C × V × f ) where:D PD CC i L CC of = input frequency in MHzif = output frequency in MHzo2∑ (C × V × f ) = sum of outputsL CC oC = output load capacitance in pFLV = supply voltage in VCC2. For HC the condition is V = GND to VI CCFor HCT the condition is V = GND to V - 1.5 VI CCORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.December 1990 2Philips Semiconductors Product specification9-bit odd/even parity generator/checker 74HC/HCT280PIN DESCRIPTIONPIN NO. SYMBOL NAME AND FUNCTION8, 9, 10, 11, 12, 13, 1, 2, 4 I to I data inputs0 85, 6 ∑ , ∑ parity outputsE O7 GND ground (0 V)14 V positive supply voltageCCFig.1 APPLICATIONS(LSTTL). They are specified in compliance with JEDECstandard no. 7A.• 25-line parity generator/checkerThe 74HC/HCT280 are 9-bit parity generators or checkers• 81-line parity generator/checkercommonly used to detect errors in high-speed dataQUICK REFERENCE DATAGND = 0 V; T =25°C; t =t = 6 nsamb r fTYPICALSYMBOL PARAMETER CONDITIONS UNITHC HCTt / t propagation delay C = 15 pF; V =5 VPHL PLH L CCI to ∑ 17 18 nsn EI to ∑ 20 22 nsn OC input capacitance 3.5 3.5 pFIC power dissipationcapacitance per package notes 1 and 2 65 65 pFPDNotes1. C is used to determine the dynamic power dissipation (P in μW):PD D2 2P =C × V × f +∑ (C × V × f ) where:D PD CC i L CC of = input frequency in MHzif = output frequency in MHzo2∑ (C × V × f ) = sum of outputsL CC oC = output load capacitance in pFLV = supply voltage in VCC2. For HC the condition is V = GND to VI CCFor HCT the condition is V = GND to V - 1.5 VI CCORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.December 1990 2Philips Semiconductors Product specification9-bit odd/even parity generator/checker 74HC/HCT280PIN DESCRIPTIONPIN NO. SYMBOL NAME AND FUNCTION8, 9, 10, 11, 12, 13, 1, 2, 4 I to I data inputs0 85, 6 ∑ , ∑ parity outputsE O7 GND ground (0 V)14 V positive supply voltageCCFig.1 pin configuration to the “180” for easy systemThe even parity output (∑ ) is HIGH when an even numberEup-gradingof data inputs (I to I ) are HIGH. The odd parity output (∑ )0 8 0• Generates either odd or even parity for nine data bitsis HIGH when an odd number of data inputs are HIGH.• Output capability: standardExpansion to larger word sizes is accomplished by tying• I category: MSICCthe even outputs (∑ ) of up to nine parallel devices to theEdata inputs of the final stage. For a single-chip 16-biteven/odd parity generator/checker, see
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