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74HC175N-74HCT175D
Quad D-type flip-flop with reset; positive-edge trigger
1. General descriptionThe 74HC175; 74HCT175 are quad positive edge-triggered D-type flip-flops with
individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is
stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and
outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are
required and the clock and master reset are common to all storage elements.
2. Features and benefits Input levels: For 74HC175: CMOS level For 74HCT175: TTL level Four edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V. Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 8 April 2014 Product data sheet
Table 1. Ordering information
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
4. Functional diagramNXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
6. Functional description[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 3. Function table[1]
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger[1] For DIP16 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
[2] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
9. Static characteristics
Table 4. Limiting values …continuedIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V)
Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0V)
Table 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Table 6. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristicsTable 7. Dynamic characteristicsGND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure11
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Table 7. Dynamic characteristics …continuedGND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure11
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC 2 fi + (CL VCC 2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC 2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
Table 7. Dynamic characteristics …continuedGND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure11
NXP Semiconductors 74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Table 8. Measurement points
