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74HC123NPHN/a247avaiDual retriggerable monostable multivibrator with reset
74HC123PWNXPN/a25550avaiDual retriggerable monostable multivibrator with reset
74HCT123PWNXPN/a13368avaiDual retriggerable monostable multivibrator with reset


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74HC123N-74HC123PW-74HCT123PW
Dual retriggerable monostable multivibrator with reset
1. General description
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods: The basic pulse is programmed by selection of an external resistor (REXT) and
capacitor (CEXT). Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ= HIGH, nQ= LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in the function table.
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
2. Features and benefits
DC triggered from active HIGH or active LOW inputs Retriggerable for very long pulses up to 100 % duty factor Direct reset terminates output pulse Schmitt-trigger action on all inputs except for the reset input ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 8 — 16 December 2011 Product data sheet
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
3. Ordering information

4. Functional diagram

Table 1. Ordering information

74HC123N 40 C to +125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT123N
74HC123D 40 C to +125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT123D
74HC123DB 40 C to +125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT123DB
74HC123PW 40 C to +125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT123PW
74HC123BQ 40 C to +125C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
SOT763-1
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset

NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning

5.2 Pin description

Table 2. Pin description
1 negative-edge triggered input 1 2 positive-edge triggered input 1
1RD 3 direct reset LOW and positive-edge triggered input 1 4 active LOW output 1 5 active HIGH output 2
2CEXT 6 external capacitor connection 2
2REXT/CEXT 7 external resistor and capacitor connection 2
GND 8 ground (0V) 9 negative-edge triggered input 2 10 positive-edge triggered input 2
2RD 11 direct reset LOW and positive-edge triggered input 2 12 active LOW output 2 13 active HIGH output 1
1CEXT 14 external capacitor connection 1
1REXT/CEXT 15 external resistor and capacitor connection 1
VCC 16 supply voltage
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH transition;  = HIGH-to-LOW transition;
[2] If the monostable was triggered before this condition was established, the pulse will continue as programmed.
7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table[1]
XXL H XL[2] H[2]
XXL L[2] H[2]   H LH
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC+ 0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO > VCC + 0.5 V - 20 mA output current except for pins nREXT/CEXT; = 0.5 V to (VCC +0.5V) 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
SSOP16 package [3]- 500 mW
TSSOP16 package [3]- 500 mW
DHVQFN16 package [4]- 500 mW
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
t/V input transition rise and
fall rate
nRD input
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC123

VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V =4mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply currentVI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
input
capacitance
-3.5 - - - - - pF
74HCT123

VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V=4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND; VCC =5.5V - - 0.1 - 1.0 - 1.0 A
ICC supply currentVI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current
per input pin; IO =0A; =VCC  2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V
pins nA, nB - 35 125 - 160 - 170 A
pin nRD - 50 180 - 225 - 245 A input
capacitance
-3.5 - - - - - pF
Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL=50 pF unless otherwise specified; for test circuit see Figure 12.
74HC123

tpd propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF;
REXT =5 k;
see Figure9
[1]
VCC = 2.0 V - 83 255 - 320 - 385 ns
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 5 V; CL = 15pF - 26 - - - - - ns
VCC = 6.0 V - 24 43 - 54 - 65 ns
nRD (reset) to nQ or nQ;
CEXT =0 pF;
REXT =5 k;
see Figure9
VCC = 2.0 V - 66 215 - 270 - 325 ns
VCC = 4.5 V - 24 43 - 54 - 65 ns
VCC = 5 V; CL = 15pF - 20 - - - - - ns
VCC = 6.0 V - 19 37 - 46 - 55 ns transition time see Figure9 [1]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns pulse width nA LOW; see Figure10
VCC = 2.0 V 100 8 - 125 - 150 - ns
VCC = 4.5 V 20 3 - 25 - 30 - ns
VCC = 6.0 V 17 2 - 21 - 26 - ns HIGH; see Figure10
VCC = 2.0 V 100 17 - 125 - 150 - ns
VCC = 4.5 V 20 6 - 25 - 30 - ns
VCC = 6.0 V 17 5 - 21 - 26 - ns
nRD LOW; see Figure11
VCC = 2.0 V 100 14 - 125 - 150 - ns
VCC = 4.5 V 20 5 - 25 - 30 - ns
VCC = 6.0 V 17 4 - 21 - 26 - ns HIGH and nQ LOW;
VCC =5.0V;
see Figure10 and 11
[2]
CEXT = 100 nF;
REXT= 10 k
-450 - - - - - s
CEXT = 0 pF;
REXT =5k
-75- - - - - ns
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset

trtrig retrigger time nA,nB; CEXT = 0 pF;
REXT = 5 k; VCC = 5.0 V;
see Figure10
[3][4] -110 - - - - - ns
REXT external timing
resistor
see Figure7
VCC = 2.0 V 10 - 1000 - - - - k
VCC = 5.0 V 2 - 1000 - - - - k
CEXT external timing
capacitor
VCC = 5.0 V; see Figure7 [4] -- - - - - - pF
CPD power
dissipation
capacitance
per monostable; = GND to VCC
[5] -54- - - - - pF
74HCT123

tPHL HIGH to LOW
propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF; REXT =
5k; see Figure9
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 5 V; CL =15pF - 26 - - - - - ns
nRD (reset) to nQ or nQ;
CEXT =0 pF;
REXT =5 k;
see Figure9
VCC = 4.5 V - 27 46 - 58 - 69 ns
VCC = 5 V; CL =15pF - 23 - - - - - ns
tPLH LOW to HIGH
propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF;
REXT =5 k;
see Figure9
VCC = 4.5 V - 28 51 - 64 - 77 ns
VCC = 5 V; CL =15pF - 26 - - - - - ns
nRD (reset) to nQ or nQ;
CEXT =0 pF; REXT =
5k; see Figure9
VCC = 4.5 V - 23 46 - 58 - 69 ns
VCC = 5 V; CL =15pF - 23 - - - - - ns transition time VCC = 4.5 V; see Figure9 [1] - 7 15 - 19 - 22 ns
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground =0 V); CL=50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset

[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2] For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid. =K REXT CEXT, where:= typical output pulse width in ns;
REXT= external resistor in k;
CEXT= external capacitor in pF;= constant = 0.45 for VCC=5.0 V and 0.55 for VCC =2.0V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7pF.
[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be
extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF,
the next formula (at VCC=5.0 V) for the setup time of a retrigger pulse is valid:
trtrig= 30 + 0.19 REXT CEXT0.9 +13 REXT 1.05, where:
trtrig= retrigger time in ns;
CEXT= external capacitor in pF; REXT= external resistor in k.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7pF.
[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT <50pF.
[5] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi+ (CL VCC2fo)+ 0.75 CEXT VCC2fo +D16 VCC where:= input frequency in MHz;= output frequency in MHz;= duty factor in %;= output load capacitance in pF;
VCC= supply voltage in V;
CEXT= timing capacitance in pF;
(CL VCC2 fo) sum of outputs. pulse width VCC = 4.5 V LOW; see Figure10 20 3 - 25 - 30 - ns HIGH; see Figure10 20 5 - 25 - 30 - ns
nRD LOW; see Figure11 20 7 - 25 - 30 - ns HIGH and nQ LOW;
VCC =5.0V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT= 10 k
-450 - - - - - s
CEXT = 0 pF;
REXT =5k
-75- - - - - ns
trtrig retrigger time nA,nB; CEXT = 0 pF;
REXT = 5 k; VCC = 5.0 V;
see Figure10
[3][4] -110 - - - - - ns
REXT external timing
resistor
VCC = 5.0 V; see Figure7 2- 1000 - - - - k
CEXT external timing
capacitor
VCC = 5.0 V; see Figure7 [4] -- - - - - - pF
CPD power
dissipation
capacitance
per monostable; = GND to VCC
[5] -56- - - - - pF
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground =0 V); CL=50 pF unless otherwise specified; for test circuit see Figure 12.
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset

NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
11. Waveforms

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